Feature Req(Perhaps a bug) for VHDL file type
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Hi,
I use NPP to modify my VHDL files and I must say that the editor is very good. I want to explain my thoughts about a bug with codes. I think this is a bug but someone can think it as a feature, whatever. This request is about the fold option while editing VHDL.
If I want to instantiate an entity in another VHDL file I can use different styles. The usual one
U0 : <something> port map
works fine with fold option, that is when I instantiate <something> the fold option (the '+' sign in that line) works fine. However with this instantiation I must include the component declaration in the VHDL file too.
Another instantiation option is like:
U0 : entity work.something port map...
or
U0 : entity something port map ...
In this example when I click to the fold button (the '+' sign near U0) all of the code is folded until the editor sees an 'end' token. This instantiation is better than the other because in that case I do not have to include the component declaration in the file. But this time fold option does not work.
I hope I could make my point. I want to clarify the situation if there are missing points.
Thanks,
Enes.
Hi,
I wanted to explain the situation with a code.
Thanks in advance.
--============================================
library IEEE;
use IEEE.std_logic_1164.all;
entity LUT is port(
a : in stD_logic_vector(7 downto 0);
b : in stD_logic_vector(7 downto 0);
clk : in std_logic
);
architecture Behavioral of LUT is
begin
-- U0, U1 and U2 declarations are
-- acceptable in VHDL and means the same
-- But folding works different for each.
-- The right one is folding of U0
U0 : example1 port map(
a => a,
b => b,
clk => clk
);
U1 : entity example2 port map(
a => a,
b => b,
clk => clk
);
U2 : entity work.example2 port map(
a => a,
b => b,
clk => clk
);
process(clk)
begin
if rising_edge(clk) then
I_CAN_WRITE <= SOMETHING_HERE;
AND_THE_PROCESS <= ENDS;
end if;
end process;
end Behavioral;