Search Results for "xact"
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Showing 7 open source projects for "xact"
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Run frontend and backend services, batch jobs, deploy websites and applications, and queue processing workloads without the need to manage infrastructure.
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Get anytime, anywhere access to your bank or credit union’s financial performance. Get insights into your bank or credit union’s financial performance from anywhere with secure, cloud-based access. Get margin components, branch performance, forecasts and more with point-and-click simplicity. Banker’s Dashboard and Credit Union dashboard integrate seamlessly with your core processor. Quick and easy setup, so you can start improving your bottom line right away. Automate reporting and eliminate errors, freeing you to focus on more value-added tasks. Quickly run and revise multiple forecast scenarios, so you can analyze variances and alternative strategies. Measure and compare branch performance. Institute best practices and hold each branch accountable for better results.
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IP-XACT 2009/2014 Platform
Smart GUI/Commandline tools to create IP-XACT( 2009/2014) files
Smart GUI to create or update IP-XACT often needed for the IP packaging. It has capability create Bus Definitions from scratch to populate BusDef library. One can create IP-XACT Component, Design or Registers by importing Ip in System Verilog/Verilog-95/VHDL, instantiate Bus Interfaces with proper port maps and attributes as needed. Smart GUI to create IP-XACT Registers, Memory Maps, Address Blocks for IP- has feature to import XLS or Verilog . It has Tcl/Python API support... -
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the...
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EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
verilog2vhdl : Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation. vhdl2verilog : Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation verilog2ipxact :Tool to create IP-XACT Component or Design from a Verilog Module. ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog Interface... -
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at https://github.com/kactus2/kactus2dev/issues... -
AudioEye is a technology company serving businesses committed to providing equal access to their online content. Transforming how the world experiences digital content, AudioEye solves issues of accessibility and enhances the user experience for the broadest audience possible. Specializing in speed to compliance with ADA-related digital accessibility requirements, AudioEye offers technology that makes digital content more accessible and more usable, for more people. Fixing digital accessibility issues starts with understanding. AudioEye continues to monitor for new issues with every site visitor, ensuring that all content is accessible to all people. You will get your first AudioEye Accessibility Score the moment you sign up. From then on, AudioEye continues to provide you a clear and actionable score quantifying your risk and identifying opportunities for improvement. AudioEye's patented technology tests for over 400 accessibility and compliance issues.
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity database... -
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CAD Flow For Design and Verification
Fronend CAD flow for IP creation, QC, IP Packaging and HandOff
... of the same IP in a SOC or SubSystem. Has hooks to facilitate integration of the IP with overrides while IP team delivers next release. Has capability to create IP-XACT Components, RGISTERS,/MemoryMap . Based upon the IP maturity, the IPQC is being run and eventually packaging and release. -
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xCAT-oms
xcat
xact
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