Search Results for "reed solomon source code"

This is a partial Java port of Reed-Solomon encoder/decoder from Phil Karn, KA9Q http://www.ka9q.net/code/fec/ (version fec-3.0.1). This mini project was born out of frustration at not being able to find a decent performing Java Reed-Solomon implementation. Only symbol sizes <= 8 are supported in this port. And testing has been performed only with GF(256) and polynomial 0x11d. As the original code was GNU Lesser General Public License (LGPL), this derivative work shall fall under LGPL...

rrenc - reads all of files which are to be written into XCD, computes an array of redundant data (usual 16-bit Solomon-Reed code) and prepares paramfile for mode2cdmaker; rrdec - reads all of files (including redundant data) from XCD and writes them to your hard disk, computes the contents of damaged sectors and insert them into proper places. Sequel of: http://forum.doom9.org/showthread.php?t=93048 http://forum.sharereactor.ru/showthread.php?t=59777

Reed-Solomon encoder/decoder for Block Devices. Provides methods for enhanced data recovery from corrupted storage media, along with faster methods for reading the data when no corruption is encountered.

A Reed-Solomon error-correcting encoder/decoder library written in C. Useful for forward error correction applications such as streaming audio, magnetic and optical storage, or just plain amusement value. GPL license with commercial license available.

Reed-Solomon codes list decoder C++ implementation

As an important linear group code in error control domain, the Reed-Solomon code has a strong capability of correcting random and sudden errors, and it is widely used in various error control systems. I implement this project to show how the code works.

A cmodel of BASEBAND PHY of Wireless system like as IEEE802.11a/b , IEEE802.16 These cmodels are writtein in C and compiled in Linux environment(gcc). Also, use "SCILAB" to analyze those models. The models includes : FFT/IFFT, OFDM, Reed-Solomon Code,

RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.