Search Results for "cache memory simulator" - Page 8

A tool for Computer Architecture students to deliver core concepts of Computer Architecture such as out-of-order execution, in-order commitment and the impact of cache misses and speculative load execution.

bMARS is a java implementation of Redcode virtual machine MARS - "Memory Array Redcode Simulator"

SiGeM is a Memory Management Software Simulator developed by Padua University's students. This software's goal is to show how processes can use memory pages, with a lot of scheduling policy provided by user configuration, in a multi-programmed system.

JPACS, Java Processor and Cache Simulator, was developed to give a simple and clear tool to simulate a processor with a complete associative memory cache at ISA level, using direct memory access or using a program written in assembly.

Procbench is a x86 CPU information tool and CPU benchmark that tests math capabilities of your processor. It will measure the performance of your CPU, FPU and the Cache/Memory subsystem.

The project will develop an in – memory object cache utilizing the LRU (least-recently-used) algorithm. The cache will store the objects that are most accessed within a fixed size memory pool. Thus system is keep statistics and calculates tradeoffs.

Java library that provides a collection of simple Object cache implementations, based on References. This library aims to facilitate the implementation of cached memory-sensitive object factories.

...For caching in .NET, refer to System.Runtime.Caching built-in library. https://docs.microsoft.com/en-us/dotnet/framework/performance/caching-in-net-framework-applications Original description: An object cache for .NET, allowing in-memory storage of arbitrary objects tospeed up network or disk access. Developers can specify an absolute expiration for objects or a maximum age that is refreshed at each access.

DSPemu emule a digital signal processor TMS320F243, with console interface showing the registers and memory. With DSPemu is possible test algorithms such as Filter, FFT/IFFT. This can be integrate and used with a circuit simulator.

Origin is a evolver for the programming game Corewars. Part of this project is a modified MARS (Memory Array Redcode Simulator) written in C especialy for evolvers. With SWIG its going to be very easy to use in different languages.

SmartCache is a cache project which provides storage facility for temporay objects in memory and disc. Main usage is in the smartclient to store temporary objects on the client side. It deals both static and non static nature of data.

JCPUSim is a CPU (Central Processing Unit) simulator written in Java. It is intended to aid in teaching how the fetch-decode-execute cycle, CPU, registers, memory and assembly programming language work in a computer system.

Mod_cachem, an Apache 2 only DSO module, creates, maintains, and manages a shared memory cache (either named or anonymous) usable by other DSO modules from within their ap_hook_method_handler.

Microprocessor simulator for the PIC16F84A on Linux using a GUI to allow for easier programming and debugging of PIC applications. Features a memory viewer, source browser, register editor and mapping PIC pins to parallel port for real world interfacing.

This is a Computer Environment Simulator, which simulates the top two parts of an operating system: Memory Management (Primary and Secondary), and Process Management. It uses paging technique to memory management, and a FCFS scheduling algorithm for proc

Full parameter test of x86 CPU's memory subsystem, including L1/L2 cache size/block size/association/write policy, L1/L2/memory bandwidth, BTB depth, RAS depth, TLB size/association and more. Best for architecture understanding purpose.

The Tiny Grasshopper Cache Store provides a memory based, least recently used (LRU), thread-safe caching mechanism that can openly cache any Java Object. The cache store is easy to use and doesn't require any setup.

SIMPLE is a computer simulator written in Java. Assembly instructions are written into the virtual memory and the processes during the execution are shown on the screen.

...The model contains 33B total parameters with only 3B activated per token, allowing it to deliver strong coding performance while remaining efficient enough to run locally on modern consumer hardware. It uses a hybrid attention architecture that combines Sliding Window Attention and global attention layers, reducing memory requirements and improving inference speed. Laguna XS.2 supports native reasoning with interleaved thinking between tool calls, enabling more capable autonomous coding agents and multi-step workflows. The model features a 262K-token context window, preserved reasoning across interactions, FP8 KV-cache optimization, and compatibility with local deployment ecosystems such as Ollama and vLLM.

A Java client for the memcached protocol with a configurable client-side in-process memory cache supporting replacement/eviction strategies (least-recently-used, least-frequently-used, first-in-first-out) designed to provide extremely low-latency lookup.

GigaChat 3 Ultra is a flagship instruct-model built on a custom Mixture-of-Experts architecture with 702B total and 36B active parameters. It leverages Multi-head Latent Attention to compress the KV cache into latent vectors, dramatically reducing memory demand and improving inference speed at scale. The model also employs Multi-Token Prediction, enabling multi-step token generation in a single pass for up to 40% faster output through speculative and parallel decoding techniques. Its training corpus incorporates ten languages, enriched with books, academic sources, code datasets, mathematical tasks, and more than 5.5 trillion tokens of high-quality synthetic data. ...