Showing 6 open source projects for "systemc"

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  • 1

    VlibTools

    Tools and libraries for use with systemc and verilog

    Tool suite and libraries for developing system-c models. Tools for managing RTL projects.
    Downloads: 0 This Week
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  • 2
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
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  • 3

    NOCEXplore

    Network-on-Chip design exploration tool based on SystemC.

    NOCEXplore is a Network-on-Chip design exploration tool based on SystemC. It includes libraries and executables for easy and fast upgradeable NoC models and a set of shell scripts. The project started during the PhD of Stefano Gigli at DII of Universita' Politecnica delle Marche (http://www.dii.univpm.it/) under the supervision of Prof. Massimo Conti and contribution of several students.
    Downloads: 0 This Week
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  • 4

    ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC...
    Downloads: 0 This Week
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  • 5
    HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
    Downloads: 0 This Week
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  • 6
    Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.
    Downloads: 0 This Week
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