Search Results for "cpu-g"

This is a simple CPU design, written in Verilog, intended for educational purposes. The objective is to provide a simulatable processor where the source code exposes concepts in CPU microarchitecture.

The Python Hardware Processsor is a implementation of a Hardware CPU in Myhdl. The CPU can directly execute something very similar to python bytecode (but only a very restricted instruction set). The Programm code for the CPU can be written directly in python (very restricted parts of python). This code is then converted by a small python programm to this restricted python bytecode. Since the hardware description is also in python, the slightly modified bytecode an then automatically loaded...

This project contains the material discussed in my PhD dissertation, entitled "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems." The source code is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/ and consists in two folders: 1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform...

Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.