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A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
This project aims to provide a basis of a good LUG organiser, including a question facility (to be solved at socials), event organiser, discussion lists, forums, and other ways to communicate with other LUG members.