Search Results for "testing tools"

Randon number generation & testing. The best suite of statistical tests for fast PRNGs anywhere. Multithreaded for speed, command line tools for automation, no upper limit on data size. Also, a variety of C++ pseudo-random number generators with well designed interfaces aimed at practical uses, not just research.

TEACUP automates many aspects of running TCP performance experiments in a specially-constructed physical testbed. TEACUP enables repeatable testing of different TCP algorithms over a range of emulated network path conditions, bottleneck rate limits and bottleneck queuing disciplines. TEACUP utilises a text-based configuration file to define experiments as combinations of parameters specifying desired network path and end host conditions. When multiple values are provided (e.g. for TCP...

... patterns). Please cite the following papers when using any image in this archive: * ASUNI N, GIACHETTI A, "TESTIMAGES: A Large Data Archive For Display and Algorithm Testing", Journal of Graphics Tools, Volume 17, Issue 4, 2015, pages 113-125, DOI:10.1080/2165347X.2015.1024298 * ASUNI N, GIACHETTI A, "TESTIMAGES: a large-scale archive for testing visual devices and basic image processing algorithms", STAG - Smart Tools & Apps for Graphics Conference, 2014.

This is a Linux command line tool to do raw I2C accesses to a bus, IF SUPPORTED BY THE ADAPTER, to probe the bus, read or write some data, detect glitches, do a bench, program an EEPROM with the required blocksize, test the I2C bus driver, ... Raw I2C mode enables data frames that are not supported by SMBus and related tools (such as i2cget, i2cset, i2cdump)

This "suite" includes a portable reference implementation and testing tools for ACP245, the automotive Telematics protocol defined by Brazil government. see: http://www.denatran.gov.br/simrav/simrav.asp

Testing complex VLSI circuits, where the whole system is integrated into a single chip called System on Chip (SoC) is very challenging due to its complexity. A SoC design consists of multiple IP cores (logic, memory, analog, high speed I/O interfaces, RF, etc.) which generally use different technologies. SoC test is the appropriate combination of test solutions associated with individual cores. Cost modelling plays a vital role in reduction of test cost and time to market. This Matlab based...

- A collection of tools for programming an Atmel AVR 8bit Microcontroler. - Circuit decriptions for Atmel AVR 8bit Microcontrolers used for testing.