Search Results for "fpga project"

Altera Quartus creates .rpt files during synthesis, place&route and bitstream generation stages of FPGA project compilation. Verification engineer checks these reports, finds warning messages and put them into own report. But big projects can contain a lot of warnings, and manual warning search is very boring and long process. That's why this parsing tool was created. This software parse report file, classifies warning types and place them into own report, where types of warnings and their row numbers in original reports are written.