A cross-platform library that gives apps easy access to USB devices
Library to enable user space application programs to communicate with USB devices
Disk Inspection and Monitoring
smartmontools contains utility programs (smartctl, smartd) to control/monitor storage systems using the Self-Monitoring, Analysis and Reporting Technology System (S.M.A.R.T.) built into most modern ATA and SCSI disks. It is derived from smartsuite.
Tool for controlling the special features of a "U3 smart drive" USB Flash disk.
Capture and control API for IIDC compliant cameras
libdc1394 is a library that provides a high level programming interface for application developers who wish to control and capture streams from IEEE 1394 based cameras that conform to the 1394-based Digital Camera Specifications (also known as the IIDC or DCAM Specifications). libdc1394 also supports some USB cameras that are IIDC compliant. Besides capture and control, libdc1394 provides a full set of colour space conversion functions (including RAW decoding), vendor specific functions and direct camera register access. Keywords: ieee1394, IIDC, DCAM, firewire, USB, machine vision, computer vision, video capture, library
Tools for flashing Rockchip devices
Tools for flashing Rockchip devices.
libmylcd is a frame & font rendering library and toolkit designed to provide low level access to 2D hardware via a video framebuffer. Supported devices include SED133x, T6963C, PCD8544, S1D15G10, USBD480, PCF8833, PCF8814, USB13700, S1D15G14.
Free MSP430 Debugger is developed in two steps : a library to provide access to the debugger hardware, and a "gdbproxy" to allow users to debug their software. This project is currently working with OLIMEX MSP430 JTAG ISO & msp430-gdbproxy.
LED Color Control System for RaspberryPi and Dreambox
Relacy is a framework for agent-oriented programming in C++. Agents are autonomous objects, they interact fully asynchronously with messages. Relacy provides means for defining user agents and messages, as well as runtime system.
Verilog Finite State Machine (FSM) Code Generator
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
This program get CPU technical information such as : vendor, name, cache,clock ...