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Hardware Software

  • WhatsUp® Gold - Start A Free 30-Day Trial WhatsUp® Gold - Start A Free 30-Day Trial Icon
    WhatsUp® Gold - Start A Free 30-Day Trial Icon

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  • OpenSOC86 Icon

    OpenSOC86

    Open implementation of the x86 architecture

    OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the bios and DOS in simulation. The system is targeted to run on the DE2-70 board. In order to run the system in hardware a SDRAM and SRAM controller need to be added. These are currently in development.

    Downloads: 12 This Week Last Update: See Project
  • The HDL Complexity Tool

    The HDL Complexity Tool parses large complex hardware projects' source code to produce useful complexity results. GOALS: 1)Practical, effective and simple 2) Integrates with existing design flows 3) Used on real projects 4) Based on existing research

  • Affordable BIOS Restoration Tool

    The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.

    Downloads: 5 This Week Last Update: See Project
  • Blowfish VHDL Core

    BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.

    Downloads: 3 This Week Last Update: See Project
  • MatlabSimulink2CPP

    Demo of Simulink to C++ C or HDL FGA for HFT potential

    Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/

    Downloads: 2 This Week Last Update: See Project
  • FPGA coprocessor floating point math lib Icon

    FPGA coprocessor floating point math lib

    libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h.

    Downloads: 1 This Week Last Update: See Project
  • High Speed Vision System

    This project aims to develop a colour-based vision processing system for use in RoboCup. We are using a CCD camera for input to an FPGA. The system locates coloured objects and outputs detected corners.

    Downloads: 1 This Week Last Update: See Project
  • ASDM-NoC

    Asynchronous Spatial Division Multiplexing Router for On-Chip Networks

    This project provide a reconfigurable asynchronous SDM router which can be configured into a basic wormhole router or an SDM router with multiple virtual circuits in every direction. Features: * 5-port router for mesh network (0 south, 1 west, 2 north, 3 east, 4 local) * The dimension order routing (XY routing) * Available flow control methods: wormhole, SDM, VC * Reconfigurable number of virtual circuits, buffer size, data width * Fully synthesizable router implementation * SystemC testbench provided Languages: * Routers are written in synthesizable SystemVerilog * Test benches are provided by SystemC Software requirements: * The open source Nangate 45nm cell library * Synopsys Design Compiler (Synthesis) * Cadence IUS -- NC Simulator (for SystemC/Verilog co-simulation)

    Downloads: 0 This Week Last Update: See Project
  • ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

    Downloads: 0 This Week Last Update: See Project
  • CPUptodate

    a micro processor 16 bits optimized to hold in a CPLD

    Downloads: 0 This Week Last Update: See Project
  • FPGADES

    This is a simple DES algorithm implemented in FPGA platform. Mainly this system was written by C and interpreted into VHDL.

    Downloads: 0 This Week Last Update: See Project
  • Free Lonworks Advanced Stack

    the goal of this project is to build a stack for Lonworks Protocol and device working on this protocol

    Downloads: 0 This Week Last Update: See Project
  • GTV SoC

    This project aims at creating an open-source SoC that will support the Google TV platform.

  • OS561/Minon/Kodek

    The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.

    Downloads: 0 This Week Last Update: See Project
  • Open WebServo

    OpenWebServo is an Open Source Hardware and Software project. Its main goal is to develop a web-controlled servo system. The project includes web application, firmware and hardware design.

    Downloads: 0 This Week Last Update: See Project
  • Palette

    Palette for computer architecture design

    Palette for computer architecture design

    Downloads: 0 This Week Last Update: See Project
  • Partially Reconfigurable Hardware

    Framework for Adaptive Hardware Concurrent Systems with DPR-FPGAs

    This project introduces new FPGA architectural tools and Linux OS modifications that aid in supporting Dynamic Partial Reconfiguration (DPR) on FPGAs for concurrent control. It shows that control systems benefit from hardware concurrency, meaning that by moving the control intelligence into hardware, the negative effects inherent to threads and their scheduler are minimized. This leaves software with the role of a high-level administrator rather than an executor, thereby eliminating unnecessary bottlenecks. The tools described in this project enable the hardware engineer to develop DPR-FPGA systems more effectively for rapid control system development. For more information, related papers and user guide, please refer to: - https://sourceforge.net/p/prhardware/wiki/Home/ - http://www2.ensc.sfu.ca/research/iDEA/personel/victor_lesau.htm

    Downloads: 0 This Week Last Update: See Project
  • RTUCR

    A Verilog design for a simple ASIC that executes the Ray Tracing Algorithm.

    Downloads: 0 This Week Last Update: See Project
  • Robert 2.Inc

    Robert 2 is a robot, but doesn't exist yet. This project intend to develop all the software to build it

    Downloads: 0 This Week Last Update: See Project
  • SUZAKU

    Project SUZAKU, home of software development based on SUZAKU FPGA board

  • Simple RISC

    Simple RISC microprocessor development project

    Downloads: 0 This Week Last Update: See Project
  • SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

    Downloads: 0 This Week Last Update: See Project
  • SystemC Logic Analyzer

    HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

    Downloads: 0 This Week Last Update: See Project
  • The SBus (Synergy Bus) Project

    The SBus is a family of high-speed packet-based databus standards, suitable for both networking and interdevice communication. They are optimized for high data density transactions. This project creates and documents the standards, schematics, and driver

  • X-RT

    X-RT: A portable multiprocessor real-time scheduling framework

    This project contains the material discussed in my PhD dissertation, entitled "Hardware/Software Design of Dynamic Real-Time Schedulers for Embedded Multiprocessor Systems." The source code is available in the SVN repository: https://sourceforge.net/p/xrt/code/6/tree/trunk/ and consists in two folders: 1) /X-RT : A portable multiprocessor scheduling framework supporting scheduling periodic real-time tasks according to the G-EDF (Global Earliest Deadline First) scheduling platform. Current version supports major POSIX systems (Linux, QNX). 2) Hardware_GEDF_Scheduler: is a hardware implementation in VHDL (targeting FPGAs) of the G-EDF multiprocessor scheduling policy.

    Downloads: 0 This Week Last Update: See Project
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