Open Source VHDL/Verilog Still Capture Software

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VHDL/Verilog Still Capture Software

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  • 1
    This is an image coder with fixed sampling, at a rate of up to 24 images per second (on XC2V1000-4 @ 40 MHz with res. up to 352x288).
    Downloads: 0 This Week
    Last Update:
    See Project
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