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Verilog processor for Notepad++. Current features:
- Instantiate a module
- Insert registers/wires from a module
- Generate a test bench template
- Automatically inserts a default header for a test bench
- Insert a clocked always block
v1.2.0 now supports ANSI and non-ANSI module declarations.
To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C.
VHDL Design Tool - code generation and project management
Application simplifies the development and management of VHDL projects. The project is displayed in a well-arranged tree structure depending on the hierarchy of entities. It also helps to maintain projects in a consistent state. Other features include automatic generation of VHDL testbenches and structures based on user-defined templates. The NetBeans platform is used as a basis for the implementation.
Its a VHDL plugin for Notepad++ which is simular with the one which is available on emacs (Copy a selcted entity port and then paste it as instatiation , Signals or as Testbench )