Showing 7 open source projects for "order"

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  • 1
    Chipyard

    Chipyard

    An Agile RISC-V SoC Design Framework with in-order cores

    Chipyard is a framework and generator for constructing custom RISC‑V SoC hardware. Built at UC Berkeley, it leverages Chisel/FIRRTL to generate full-stack systems—from CPU cores to peripherals—and includes simulators, FPGA deployment tools, and integration with Rocket Chip and other RISC‑V ecosystems.
    Downloads: 0 This Week
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  • 2
    tapir

    tapir

    Declarative, type-safe web endpoints library

    ...Is your company already using tapir? We're continually expanding the "adopters" section in the documentation; the more the merrier! It would be great to feature your company's logo, but in order to do that, we'll need to write permission to avoid any legal misunderstandings.
    Downloads: 0 This Week
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  • 3
    XiangShan

    XiangShan

    Open-source high-performance RISC-V processor

    XiangShan is an open-source, high-performance RISC-V processor project that implements out-of-order superscalar cores using Chisel for hardware construction. The design targets modern performance goals—deep pipelines, speculative execution, multi-issue decode/execute, and sophisticated branch prediction—while remaining synthesizable for ASIC flows and portable to FPGAs for research. A modular microarchitecture separates frontend, backend, and memory subsystems with coherent caches and scalable interconnects, enabling multi-core configurations. ...
    Downloads: 0 This Week
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  • 4
    Rocket Chip

    Rocket Chip

    Rocket Chip Generator

    Rocket Chip is a parameterized RISC-V SoC generator written in Chisel that produces synthesizable RTL for a wide range of cores and configurations. At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. ...
    Downloads: 1 This Week
    Last Update:
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  • 5
    RISC-V BOOM

    RISC-V BOOM

    SonicBOOM: The Berkeley Out-of-Order Machine

    The riscv-boom project (also called BOOM or SonicBOOM) implements a high-performance, synthesizable out-of-order RISC-V core written in the Chisel hardware construction language. It targets the RV64GC (i.e. 64-bit with general + compressed + floating point) instruction set and supports features such as virtual memory, caches, atomics, and IEEE-754 floating point. The design is parameterizable, meaning users can tune pipeline widths, buffer sizes, functional units, and other microarchitectural knobs to explore tradeoffs. ...
    Downloads: 0 This Week
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  • 6
    Scaloid

    Scaloid

    Scaloid makes your Android code easy to understand and maintain

    ...For example, it offers DSL-style helpers for defining views and layouts with less boilerplate, implicit conversions to help with event listeners, and utility methods to simplify common tasks. Scaloid aims to capture the expressiveness of Scala—higher-order methods, implicit conversions, extension methods—to let Android development be more functional and succinct. It lowers friction for Scala developers targeting Android, making UI code more compact and composable while still maintaining access to full Android platform capabilities.
    Downloads: 0 This Week
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  • 7
    Gizzard

    Gizzard

    Framework for creating eventually-consistent distributed datastores

    Gizzard is a Scala framework originally developed by Twitter for building scalable, fault-tolerant, distributed key-value stores that can be sharded and replicated. It provides infrastructure for routing requests through shard trees, splitting or rebalancing shards dynamically, failover, and migrations. In Gizzard, data is stored in underlying storage shards (which could be databases or other stores) and Gizzard handles the process of routing requests correctly as the cluster topology...
    Downloads: 0 This Week
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