Search Results for "cache memory simulator"

...At its heart is the Rocket core, a simple, in-order, five-stage RISC-V implementation, but the generator composes much more: coherent caches, MMUs, interrupt controllers, and buses via the TileLink interconnect. A diplomacy framework (LazyModules) lets designers wire components with negotiated parameters, enabling reuse and rapid exploration of different cache sizes, port counts, and memory hierarchies. The generator supports custom accelerators through the RoCC interface, allowing domain-specific compute units to be plugged into the pipeline with shared cache and memory semantics. Tooling integrates with FIRRTL, Verilator, and commercial EDA flows, and the ecosystem around Rocket Chip (e.g., Chipyard) adds harnesses, peripherals, and verification infrastructure.