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Package manager and build abstraction tool for FPGA/ASIC development
FuseSoC is a package manager and build abstraction tool for hardware description language (HDL) code, aimed at simplifying the development and reuse of IP cores. It provides a standardized way to describe, manage, and build hardware projects, facilitating collaboration and reducing duplication of effort in FPGA and ASIC development.
Repurposing existing HDL tools to help writing better code
HDL Checker is a language server that wraps VHDL/Verilg/SystemVerilog tools that aims to reduce the boilerplate code needed to set things up. It supports Language Server Protocol or a custom HTTP interface; can infer the library VHDL files likely to belong to, besides working out mixed language dependencies, compilation order, interpreting some compiler messages and providing some (limited) static checks.