Search Results for "test hardware"
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Showing 9 open source projects for "test hardware"
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1
GNSS-SDR
An open source software-defined GNSS receiver
An open source software-defined Global Navigation Satellite Systems (GNSS) receiver written in C++ and based on the GNU Radio framework. -
2
AnCH Framework
Another C++ Hack
This project has been migrated to GitHub : https://github.com/vlachenal/anch-framework AnCH framework aims to provide utility classes for some common programming features. Features are implemented to be used as simply as possible. This framework was initially a way to test new C++ specifications (C++11) and to test C++ design patterns and tricks. Only POSIX systems are supported for now. Others could be supported later. (Partial) Doxygen documentation can be found on project home page. -
3
Qfsm
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation. -
4
MatlabSimulink2CPP
Demo of Simulink to C++ C or HDL FGA for HFT potential
Video and files download for Visual trading idea to C++ or FPGA HFT Meetup File download sample: test model (Matlab 2014b with Visual Studio 2013 C++ project generated) Powerpoint MATLAB SIMULINK http://quantlabs.net/blog/2015/04/video-and-files-download-for-visual-trading-idea-to-c-or-fpga-hft-meetup/ -
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5
msp4linux
C++ based debug interface to MSP430, MSP-FET430UIF needed
... of the PC <> UIF transfer protocol and a public interface for a simulated target. The screen shot demonstrates a simulated MSP430F5438A target on CCS (linux). As long as the CCS instance is not aware that there is no real hardware attached, it's a good test option for external simulators. -
6
FPGAsm
Create fast bare-metal FPGA designs without Verilog or VHDL
... testing and physical test harness creation, radically changing the workflow. FPGAsm offers you an opportunity to REALLY understand Xilinx FPGAs, create circuits DIRECTLY on the FPGA using an opensource tool, and share your knowlege and projects with the community. Supported architectures: Xilinx (via xdl) -
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Real time micro benchmark multi-lingual suite (RTMB) provides a good way to measure the deterministic quality of hardware, an operating system, or a Java Virtual Machine. RTMB consists of benchmarks in C, C++ and Java
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PC-TEST is a hardware detecting & testing tool (detection, benchmark, stress-test, S.M.A.R.T., etc.). It is developed to run on any Intel x86 compatible PC (including 8086 PC/XT). It runs perfectly under DOS but compatible with Windows & DosEmu.
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9
BP-Sim
EFT simulator
... transaction load up to 2000 TPS. BP-Sim HSM module provides an adequate TCP/IP simulation of the Thales Hardware Security Mod. BP-SeeEMV simulates the steps involved in an EMV transaction that take place in the EMV terminal and the Issuer Server (when conducted online). Module can process a transaction one step at a time in step-by-step mode or to certain break-point. -
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