3 projects for "verilog compiler" with 2 filters applied:

  • MongoDB Atlas runs apps anywhere Icon
    MongoDB Atlas runs apps anywhere

    Deploy in 115+ regions with the modern database for every enterprise.

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  • 1
    XLS

    XLS

    XLS: Accelerated HW Synthesis

    XLS is an open-source toolkit for building high-level hardware with a modern compiler stack that spans from a functional DSL to optimized IR and hardware generation. At the front end, DSLX lets you describe algorithms with strong typing and familiar control flow while remaining synthesis-friendly. The compiler lowers DSLX into a rich intermediate representation, applies aggressive optimization and scheduling passes, and can either JIT the design for software simulation or emit Verilog for FPGA/ASIC flows. ...
    Downloads: 1 This Week
    Last Update:
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  • 2
    Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
    Downloads: 0 This Week
    Last Update:
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  • 3
    Qfsm

    Qfsm

    A graphical Finite State Machine (FSM) designer.

    A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
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    Downloads: 58 This Week
    Last Update:
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