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Showing 2 open source projects for "systemverilog"

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    smPla

    SystemVerilog module to substitute Verilog PLA system tasks.

    SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane.
    Downloads: 0 This Week
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  • 2
    xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
    Downloads: 0 This Week
    Last Update:
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