Showing 2 open source projects for "file::rsyncp"

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  • 1
    VSYML is an automated symbolic simulator for VHDL designs.
    Downloads: 0 This Week
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  • 2
    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.
    Downloads: 0 This Week
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