Open Source VHDL/Verilog Simulation Software

This directory contains the sources of GHDL, the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language (HDL). GHDL is not an interpreter: it allows you to analyze and elaborate sources for generating machine code from your design. Native program execution is the only way for high-speed simulation. Full support for the 1987, 1993, 2002 versions of the IEEE 1076 VHDL standard, and partial for the 2008 and 2019 revisions. By using a code generator (LLVM, GCC or, x86_64/i386 only, a built-in one), it is much faster than any interpreted simulator. It can handle very large designs, such as leon3/grlib. GHDL runs on GNU/Linux, Windows and macOS; on x86, x86_64, armv6/armv7/aarch32, aarch64 and ppc64. You can freely download nightly assets, use OCI images (aka Docker/Podman containers), or try building it on your own machine.

FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

SystemVerilog module that models the following PLA system tasks of Verilog: $a/sync$and$array $a/sync$nand$array $a/sync$or$array $a/sync$nor$array $a/sync$and$plane $a/sync$nand$plane $a/sync$or$plane $a/sync$nor$plane.

Development of a fully designed alarm clock implemented on the Xilinx Spartan3 board.

Custom uav is a complete flight control system in development. The project includes everything required for unmanned flight.

Labcoat for SuperWikia Alpha fabrication manages new or revised fabrication processes. Its 'Cleanroom' applets allow codesmiths to access the lab environment, used to create semiconductors, substrate prototypes, chipset instruction blocks and other Labcoat projects. Our extensions in future releases will include UML support for C#/C++ conforming projects, import/export architecture schematics and refactoring sub-projects.

VSYML is an automated symbolic simulator for VHDL designs.

Tool-independent Makefile generator for VHDL models.

xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.

SFENCE Extension Library (SEL) for access verilog function via PLI/VPI API to calls of standard SFENCE Function_Function objects.

vcd2svg can parse Value Change Dump (VCD) files and draw an impulse diagram using Scalable Vector Graphics (SVG). It works together with the GHDL open-source simulator.

A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

This library supports interoperability between components written for different verification methodologies such as VMM and OVM. This is maintained by the Accellera Verification Intellectual Property Technical Subcommittee.