Search Results for "bus"
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Showing 5 open source projects for "bus"
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Virtual Motherboard
Plug&Play Hardware simulation over a virtual bus system.
The Virtual Motherboard provides a specification of a TCP/IP based system bus, a motherboard simulator implementing this specifaction, and a collection of reusable device simulators. It is the perfect start to build new custom hardware simulators. -
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SystemC Network Simulation Library (SCNSL) is an extension of SystemC to allow modelling packet-based networks such as wireless networks, ethernet, fieldbus, etc. As done by basic SystemC for signals on the bus, SCNSL provides primitives to model packet trasmission, reception, contention on the channel and wireless path loss. The use of SCNSL allows the easy and complete modelling of distributed applications of networked embedded systems such as wireless sensor networks, routers, and distributed plant controllers. SCNSL has migrated: please go to GitLab for the latest version: https://gitlab.com/open-kappa/scnsl
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jCircuits
An easy-to-use Simulation of Hardware-Gates
A very easy-to-use but complex Gate-Simulation.You can simulate various gatters like AND, NAND, OR, NOR, NOT, XOR. And also build Flip-Flops, Full Adders and other compley structures. In other words its a register-Transfer Simulation of Hardware-Processes. There are also 2 Applet-Versions - the full Version and a only-Display-Version ---------- USEFUL TIPS: ---------- Always enter the Edit-Mode (swiss knife) bevor editing something ;) [!! IMPORTANT !!] Try out the... -
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Experimental software for timetabling Bus Rapid Transit systems highly efficiently. Also has a number of generic function for manipulating transport data, and so may be convertible to other uses.
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An easy to install and use toolbox for octave for the calculation purpose of power system along with features like Economic load dispatch, load flow analysis, transmission line parameter and swing equation etc
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