Search Results for "latency"

JDiskMark is a powerful and versatile disk benchmarking tool written in Java, designed to help measure the performance and health of your storage drives. Whether you're testing HDDs, SSDs, or network locations, JDiskMark provides reliable insights into your disk's read and write...

Live Transcribe Speech Engine provides on-device speech recognition components that power real-time transcription for accessibility and everyday voice-first experiences. Its design prioritizes latency and robustness in noisy, far-field environments, enabling continuous transcription with low delay on mobile hardware. The engine manages audio front-end processing—such as noise suppression and voice activity detection—before feeding audio into compact, accurate acoustic and language models. Partial hypotheses stream as words are recognized, then stabilize with minimal jitter as confidence increases, which is crucial for usability. ...

...It is a simplified version of Corvis [Jones et al.,Tsotsos et al.], designed for pedagogical purposes, and incorporates odometry (relative motion of the sensor platform), local mapping (pose relative to a reference frame of the oldest visible features), and global mapping (pose relative to a global frame, including loop-closure and global re-localization, this feature, present in Corvis, is not yet incorporated in XIVO). XIVO runs at 140FPS on stored data (here from a RealSense D435i sensor) or on live streams with a latency of around 1-7ms, depending on the hardware. It takes as input video frames from a calibrated camera and inertial measurements from an IMU and outputs a sparse point cloud with attribute features and 6 DOF pose of the camera. It performs auto-calibration of the relative pose between the camera and the IMU as well as the time-stamp alignment.

...FastFlow run-time is built upon non-blocking threads and lock-free queues. Thanks to its very efficient CAS-free communication/synchronization support (e.g. few clock cycles core-to-core latency), FastFlow effectively supports the exploitation of fine grain parallelism, e.g. parallel codes managing very high frequency streams on commodity multi-core. FastFlow works on x86, x86_64, PPC, ARM, and Linux, Mac and Win XP/7. From Jan 1, 2018 code development migrated on GitHub at https://github.com/fastflow/fastflow

darc, the Durham Adaptive optics Real-time Controller. For documentation or darctalk client only, select "View all files". For the latest bleeding-edge version, please use: git clone git://git.code.sf.net/p/darc2/code darc (no password required) (this changed May 2013 due to a sourceforge update). If you use darc, please cite with: Basden, A and Myers, R, MNRAS Vol 242, page 1483, 2012

...The framework supports multiple target platforms within a distributed heterogeneous environment. It offers optimized device code on the backend side, high scalability through latency hiding and asynchronous execution across multiple nodes. LAMA's modular and extensible software design supports the developer on several levels, regardless of whether writing his own portable code with the Heterogeneous Computing Development Kit or using prepared functionality from the Linear Algebra Package, the user always gains high productivity and maximum performance.

We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. ...

A networks-on-chip (NoC) simulator allows designers to early estimate performance (latency and throughput), energy efficiency (average/peak power, average energy per packet) and area of several networks on-chip configurations at different CMOS nodes. This tool is a cycle-accurate simulator and is open-source using SystemC, a C++ plugin, which is used to quickly model complex systems at a higher level but less details than RTL.

Low-latency high speed hybrid framework-library for utilizing the IBM Cell processor SPE units (PS3, QS20) to carry out computational tasks. Provides some DSP tasks such as FFT and complex MAC. Thread-safe and easily extensible with new arithmetics tasks

OpenDMTP is a protocol/framework that allows communications with small devices (mobile phones, PDA's, and other high-latency/low-bandwidth devices), especially geared towards the transmission of GPS, temperature, and other remote monitoring information.

Bandwidth Apart is a simulation used to estimate bandwidth usage over communication links in the telecommunication industry. It also has the ability to ping VoIP servers and test connections for latency, packet loss, jitter etc...