Search Results for "free memory"
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Showing 8 open source projects for "free memory"
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Autshumato ITE
Free CAT tool based on OmegaT.
Autshumato Integrated Translation Environment is a free computer aided translation application. It provides a single translation environment that contains translation memory, machine translation and a glossary to facilitate the translation process. The Autshumato ITE is a derived work of the popular OmegaT CAT tool; customised for the South-African environment. -
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bel_fft
FFT co-processor in Verilog based on the KISS FFT
bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and... -
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FastPval is multiple stage p-value computing software that computes empirical p-values from a large set of permutated/resampled background data.
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An open-source desktop application for load/performance testing a web site. It has a very simple UI to configure the load test. The future plan includes transaction support, record, playback and support for load injector agents.
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MongoDB Atlas runs apps anywhereMongoDB Atlas gives you the freedom to build and run modern applications anywhere—across AWS, Azure, and Google Cloud. With global availability in over 115 regions, Atlas lets you deploy close to your users, meet compliance needs, and scale with confidence across any geography.
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It's a utility application for updating and integrating translation memories, created by the Autshumato ITE, over a network. Licensed under the TMate Open Source License and free to download and be used by anyone.
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JPACS, Java Processor and Cache Simulator, was developed to give a simple and clear tool to simulate a processor with a complete associative memory cache at ISA level, using direct memory access or using a program written in assembly.
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A basic MIPS simulator based on DEVS (Discrete Event System Specification). This project aims to develop the behavior of some components of the MIPS architecture (Registers, Memory, Muxs) including only seven instructions (add, sub, and, or, lw, sw, beq)
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