Search Results for "cache memory simulator"

MGSyn (Model, Game, Synthesis) is an open-source tool which integrates game-based synthesis into model-driven development for industrial control and automation. It is served for research and educational purposes. MGSyn has been originally developed by Department of Informatics (Unit 6), TU München and fortiss GmbH and is now maintained by fortiss GmbH. The software is released under the GNU General Public License Version 3.0 (GPLv3). Please download the tutorial for step-by-step...

...The significant advance of this project over previous work is the global nature of simulation, the memory and performance requirements of which motivate us towards a multi-core, multi-computer solution.

This is an IDE for 8051 which can be used to write and simulate assembly language program and find out errors if any. The project implements almost all 8051 functions. It visually shows the content of all register and memory.

Bloft (BLObby and sOFT) is a real-time soft-body physics simulator optimized for real-world mobile phones. It is written in Java and uses fixed-point math only. Memory allocations are minimized to suite the needs of JVMs in older mobile phones.

SiGeM is a Memory Management Software Simulator developed by Padua University's students. This software's goal is to show how processes can use memory pages, with a lot of scheduling policy provided by user configuration, in a multi-programmed system.

JPACS, Java Processor and Cache Simulator, was developed to give a simple and clear tool to simulate a processor with a complete associative memory cache at ISA level, using direct memory access or using a program written in assembly.

JCPUSim is a CPU (Central Processing Unit) simulator written in Java. It is intended to aid in teaching how the fetch-decode-execute cycle, CPU, registers, memory and assembly programming language work in a computer system.

A basic MIPS simulator based on DEVS (Discrete Event System Specification). This project aims to develop the behavior of some components of the MIPS architecture (Registers, Memory, Muxs) including only seven instructions (add, sub, and, or, lw, sw, beq)