Search Results for "test case generation tool"

A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.

This software and hardware system adapts your 92-95 Honda diagnostic port to an OBD II standard port, readable by any generic scan tool. In 1996 the federal government along with the state of California mandated that all cars be equipped with comprehensive emissions reduction equipment and a standardized emissions diagnostic system. Before this year, each independent vehicle manufacturer had its own proprietary, undocumented diagnostic interface. These interfaces provide essential...

FPGAsm is a low-level alternative to verilog and VHDL. A near-instant 'assembler for FPGAs', this simple yet powerful language facilitates bottom-up design, layout and wiring of modules, and generation of .xdl output. With about 10 keywords to learn, you can start making circuits in minutes. Now you can focus on learning the ins and outs of the FPGA instead of complex tools and languages. Fast turnaround time and bottom-up approach invite exploration, experimentation, live circuit testing and physical test harness creation, radically changing the workflow. ...

Tailorshop: Optimization based Analysis and data Generation tOol. Support tool for the computer test scenario "Tailorshop" that is the basis for many psychological studies. Data can be generated, visualized, and provided to optimization solvers.