Scientific/Engineering Software

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Scientific/Engineering Software

  • Focus on your Business with an integrated Business Cloud Focus on your Business with an integrated Business Cloud Icon
    Focus on your Business with an integrated Business Cloud Icon

    Reliable & Secure Communications Systems

    • 90+ features: video, file management, cloud phones
    • 99.999% financially backed uptime SLA
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  • Get the Edge; Toad Edge Get the Edge; Toad Edge Icon
    Get the Edge; Toad Edge Icon

    Your next-gen toolset for MySQL database environments

    If your organization takes advantage of the cost-effective, flexible MySQL open source database platform, then you need a toolset that supports your commitment to open source relational databases.  Toad Edge for MySQL has what you need and helps you ramp up on MySQL quickly, ensuring faster time to value.
  • Icarus Verilog

    Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.

  • ghdl-updates

    GHDL - a VHDL simulator

    GHDL is the leading open source VHDL simulator. *** Now on github.com/tgingold/ghdl *** We have binary distributions for Debian Linux, Mac OSX and Windows. On other systems, getting GHDL from here means downloading the current source package and building GHDL from source. Alternatively you can get the latest source version (warning : occasionally unstable!) by pulling a snapshot from the git repository.

  • adms Icon

    adms

    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

  • VeriWell Verilog Simulator

    VeriWell is a full Verilog simulator. It supports nearly all of the IEEE1364-1995 standard, as well as PLI 1.0. Yes, VeriWell *is* the same simulator that was sold by Wellspring Solutions in the mid-1990 and was included with the Thomas and Moorby book

  • Welec W2000a

    Firmware development/ improvement for the digital storage oscilloscope "Welec 2000a- series".

  • Locate Sensitive Data across Networks and Workstations Locate Sensitive Data across Networks and Workstations Icon
    Locate Sensitive Data across Networks and Workstations Icon

    Build the Business Case for Effective Security Investments

    Your customers recognize the importance of security, but often don’t realize the urgency until they see something tangible. SolarWinds Risk Intelligence assigns value to your data vulnerability, helping you build a strong business case for data protection and triage the most important problems to tackle. Some powerful features include data risk communicated as financial impact, at-risk data discovery and PCI DSS, PAN & PII scans.
  • VHDL Notepad++ Plugin

    VHDL Plugin for the Notepad++ Editor

    VHDL plugin based on http://sourceforge.net/projects/nppvhdlplugin/ This version is enhanced to include: - Insert Instantiation - Insert Signals - Create Test Bench Framework - Insert Component - Make comments Doxygen compliant - Create New Behavioral/Structural Entity Template - Create New Package File Template - Insert Synchronous Process - Insert Asynchronous Process - Insert a Default Header The default header is set in the vhdlConfig.txt file.

    Downloads: 95 This Week Last Update: See Project
  • Notepad++ Verilog Plugin

    Verilog plugin for Notepad++

    Verilog processor for Notepad++. Current features: - Instantiate a module - Insert registers/wires from a module - Generate a test bench template - Automatically inserts a default header for a test bench - Insert a clocked always block v1.2.0 now supports ANSI and non-ANSI module declarations. To use this plugin, select the module declaration (including parameter and I/O definitions below for non-ANSI) and click SHIFT-CTRL-C. This selects the module and parses its components. After this, all other functions are available.

    Downloads: 77 This Week Last Update: See Project
  • bel_fft Icon

    bel_fft

    FFT co-processor in Verilog based on the KISS FFT

    bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

  • pyrpl

    PyRPL turns your Red Pitaya into a powerful analog feedback device.

    The Red Pitaya is a commercial, affordable FPGA board with fast analog inputs and outputs. This makes it useful for quantum optics experiments, in particular as a digital feedback controller for analog systems. Based on the open source software provided by the board manufacturer, PyRPL (Python RedPitaya Lockbox) implements many devices that are needed for optics experiments with the Red Pitaya. PyRPL implements various digital signal processing (DSP) modules (see features below). It allows to arbitrarily interconnect the available DSP modules and retrieve signal values on timescales below 1 ms. The graphical user interface (GUI) provides a realtime display of the various measurement instruments and allows the easy configuration of DSP signal chains and feedback controllers. At the highest abstraction level, arbitrary feedback sequences can be defined to fulfill tasks as complex as approaching and locking a resonance of a high-finesse Fabry-Perot cavity (tested up to finesse=100,000).

    Downloads: 32 This Week Last Update: See Project
  • OpenSOC86 Icon

    OpenSOC86

    Open implementation of the x86 architecture

    OpenSOC86 is an open implementation of the x86 architecture in Verilog. The current version only implements the 16-bit part (real mode). The processor is a pipelined architecture clocked at 100 MHz in a Cyclone II speed grade -6. Therefore it can be seen as similar to a 486 in real mode. Several peripherals are also implemented in a somewhat minimalistic way, but enough to be able to boot an IBM PCXT compatible bios and MSDOS 6.22. The current implementation is only proven to boot the bios and DOS in simulation. The system is targeted to run on the DE2-70 board. In order to run the system in hardware a SDRAM and SRAM controller need to be added. These are currently in development.

    Downloads: 12 This Week Last Update: See Project
  • DigitalOcean - The Total Cloud Computing Platform DigitalOcean - The Total Cloud Computing Platform Icon
    DigitalOcean - The Total Cloud Computing Platform Icon

    Our platform was built with simplicity at the forefront, so developers can build and deploy with ease.

    DigitalOcean's predictable format removes infrastructure friction and allows developers more time to build software customers love. Easily deploy, manage, and scale applications of any size. DigitalOcean also provides the support you need with hundreds of in-depth tutorials and an active online community.
  • MiniLA - logic analyzer SW & HW

    MiniLA logic analyzer software and hardware

    Downloads: 9 This Week Last Update: See Project
  • Pulse Programmer Icon

    Pulse Programmer

    A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.

  • FSMDesigner Icon

    FSMDesigner

    FSMDesigner is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. FSMDesigner4 uses the Simple-Moore FSM model guaranteeing efficient fast complex control circuits.

    Downloads: 7 This Week Last Update: See Project
  • GPS to Radio-controlled Clock Icon

    GPS to Radio-controlled Clock

    GPS to Radio-controlled Clock

    The purpose of this simple DIY project is to build an electronic circuit that received the GPS time signal, convert it to the radio-controlled clock format, and transmit that signal to the clock. Once built, there is no need for setup and maintenance, all you need is put this unit close to the window to receive GPS signal, and it will transmit the time signal to your radio-controlled clock.

  • Project 2306 IDE Rad MacOS MCU DeveR Icon

    Project 2306 IDE Rad MacOS MCU DeveR

    Electronic design and programming tools suite like Eagle, MpLab

    Currently Only MacOS is Present, PreAlpha means not Ready to use, Application is provided Without Strict Garantee, License not OSI. All others platform Windows, Linux, HaikuOS STILL under TEST, Dummy "Hello world" is provided instead Project2306 IDE : Application pour la programmation de Microcontroleurs et d' Application Electronique Project2306 IDE : for All whom want to Create and Develop on Embed Platform Software as Programming Tools suite and PCB Design Planned Features : Similar with mainstream market tools IDE and GUI Wrapper like : LabView©, Proteus©, MPLab©, Eagle CAD©, Tools Suite for Most Market Microcontroller. Tools suite for Arduino, Pinguino, Pic, AVR, ARM, Basic Stamp, Risc, other platform Fully Integrated IDE. Adobe PDF Help section SQL Connectivity Community Avail : https://www.facebook.com/Project-Core-2306-Nextgen-Eda-pcbradide-for-Mcumacoslinuxwindows-138250749681138/?fref=ts

    Downloads: 5 This Week Last Update: See Project
  • lpACLib

    An Open-Source Library for Low-Power Approximate Computing Modules

    The “lpACLib” library contains the VHDL description of accurate and approximate versions of several arithmetic modules (like adders and multiplier of different bit-widths) and accelerators. Moreover, it also provides the corresponding software behavioral models/implementations developed in C and MATLAB to enable quality characterization. Besides our novel designs, it also contains implementations for several state-of-the-art arithmetic modules and their approximate versions. This open-source library facilitates research and development in approximate computing at higher abstraction levels, and to facilitate reproducible research and comparisons. In case of usage, please refer to our publication: Muhammad Shafique, Rehan Hafiz, Semeen Rehman, Walaa El-Harouni, Jörg Henkel, "Cross-Layer Approximate Computing: From Logic to Architectures", Design Automation Conference (DAC), 2016. Contributors: Authors, Vanshika Baoni, M. Abdullah Hanif http://ces.itec.kit.edu/lpACLib.php

    Downloads: 5 This Week Last Update: See Project
  • Anie

    PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e

    Embedded system design (VHDL description) based on Xilinx's Spartan3E Development Kit to perform real-time PID control and monitoring of time critical plants such as brushless DC motors, maglevs... vimeo.com/channels/anie prezi.com/gpbycavq499c/anie/

    Downloads: 4 This Week Last Update: See Project
  • Affordable BIOS Restoration Tool

    The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.

    Downloads: 3 This Week Last Update: See Project
  • Blowfish VHDL Core

    BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.

    Downloads: 3 This Week Last Update: See Project
  • Verilog Tool Framework

    vrq is verilog parser that supports plugin tools to process verilog. Current plugins include tools to perform x-propagation and to auto build hiearchy.

    Downloads: 2 This Week Last Update: See Project
  • ApproxAdderLib

    Library of Approximate Adders

    We provide MATLAB and Verilog Models of GeAr, and previously proposed adders (ACA-I, ETAII, ACA-II and GDA) at http://sourceforge.net/projects/approxadderlib/ GeAr is a low latency Generic Accuracy Configurable Adder that provides a higher number of potential configurations compared to state-of-the-art approximate adders, thus enabling a high degree of flexibility and trade-off between performance and output quality. These MATALB and Verilog models can allow software programmer as well as hardware designers to evaluate their code and design. To the best of our knowledge, this is the first open-source library of approximate adders that facilitates reproducible comparisons and further research and development in this direction across various layers of design abstraction. This work is a result of collaborative effort between Chair for Embedded Systems (CES) at Karlsruhe Institute of Technology (KIT), Germany and Vision Image and Signal Processing (VISpro) Lab at SEECS-NUST, Pakistan.

    Downloads: 1 This Week Last Update: See Project
  • FPGA coprocessor floating point math lib Icon

    FPGA coprocessor floating point math lib

    libhdlfltp is a VHDL library of floating point operators, all of which are parametrized, synthesizable to FPGAs and cover a number of the core operators in math.h.

    Downloads: 1 This Week Last Update: See Project
  • verilog compiler

    A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.

    Downloads: 1 This Week Last Update: See Project
  • A UPF script 2 CPF script converter

    upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.

  • Alarm clock

    Development of a fully designed alarm clock implemented on the Xilinx Spartan3 board.

    Downloads: 0 This Week Last Update: See Project
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