Real Time Electronic Circuit Simulator.
Real Time Electronic Circuit Simulator. Include PIC, AVR and Arduino simulation. Code Editor & Debugger for Arduino, GcBasic, PIC asm, AVR asm. AVR simulation provide by simavr: https://github.com/buserror/simavr PIC simulation provided by GpSim: http://gpsim.sourceforge.net/
Simple and intuitive 2D vector drawing for electronics and not only.
A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the development live on Twitter: https://twitter.com/davbucci
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
The Future of the Java Circuit Simulator
Circuitmod is a circuit simulator that extend the capacity of the original Falstad's Java Circuit Simulator into CMOS Chips, Led Arrays, Led Matrix and PIC Programming. The Horizon is limitless. Try today.
Gerber to PDF converter
Gerber2PDF is a command-line tool to convert Gerber files to PDF for proofing and hobbyist printing purposes. It converts multiple Gerber files at once, placing the resulting layers each on it's own page within the PDF. Each layer has a PDF bookmark for easy reference. Layers can optionally be combined onto a single page and rendered with custom colours and transparency. There is a Drill to Gerber converter available from the downloads page.
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
Qt based Veroboard, Perfboard, and PCB layout and routing application
Cross-platform software for producing Veroboard (stripboard), Perfboard, and single-sided PCB layouts. Automatically prevents short circuits and checks for open circuits. Built using the Qt cross platform library, and tested on Linux (32-bit and 64-bit) and on Windows 7 (32-bit and 64-bit). Precompiled versions available for Windows 7 (32 bit and 64 bit) and for 64-bit Linux Mint 18.3 (Cinnamon/MATE/Xfce/KDE).
QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.
AVR simulator IDE
Electronic circuit simulator. Simple environment to run and debug firmware for AVR 8-bit microprocessors. Able to run arduino firmware. Internally this program uses the open source Simavr AVR Processor Simulator (https://github.com/buserror/simavr) and wraps all its functions in a GUI shell. Setups for firmware debugging scenarios can be created dynamically. Able to run 16MHz MCU with decent set of external parts in real time. In particular this can be used for development of CNC firmware in conjuction with its CAM frontend without access to the real hardware. For Linux and Windows systems. Please visit wiki pages (https://sourceforge.net/p/simutron/wiki/Home/) for instructions
A calculation tool for the MC34063
If you ever worked with the MC34063 Switching Controller, you know what a pain it is to calculate all the part values. This tool is an universal tool to help you with this process. You can calculate any standard application, such as step-up, step-down, inverting and step-up-down. PS: I would be happy about any (positive xD) reviews as well as any bugreports, comments or feature requests that you might have!
FIBEX format viewer and navigator
Das Field Bus Exchange Format (FIBEX) ist ein XML-Austauschformat für diverse Bussysteme in vernetzten Fahrzeugen. Der Inhalt praxisrelevanter FIBEX-Dateien ist ohne entsprechende Toolunterstützung nur schwer zu fassen. Der FIBEXplorer® bietet einen vielseitigen Viewer für das FIBEX-Format. 100% FIBEX FIBEX Vergleich Linkverfolgung Working Sets Vertikale Navigation Clustered Navigation Startup Wizard By courtesy of Sulzer GmbH (http://www.sulzer.de)
lilpM32 is a MIPS-like processor designed in Logisim, assembler program and documentation for them. Complete assembler and fully functional instruction set with I/O and subroutines features allow to write full-blown complicated programs.
IEC 104 server and client simulator, Source code Library, win, Linux
IEC 60870-5-104 FreyrSCADA offering 1) IEC104 Server Simulator 2) IEC104 Client Simulator 3) Static and Dynamic Libraries 4) IEC104 Source Code Library 5) Demo Kit (Raspberry Pi & BeagleBone Black) or Customer specific Hardware windows, Linux, QNX Download Evaluation Kit - IEC 60870-5-104 Development Bundle New updated Version of IEC 60870-5-104 Simulator & SDK (Software Development Kit) is available now. FreyrSCADA IEC-60870-5-104 Development Bundle v21.03.026 In the Development Bundle, We included IEC 60870-5-104 Server & Client Simulator, Windows & Linux SDK. http://www.freyrscada.com/iec-60870-5-104.php http://www.freyrscada.com/iec-60870-5-104-Server-Simulator.php http://www.freyrscada.com/iec-60870-5-104-Client-Simulator.php http://www.freyrscada.com/iec-60870-5-104-Windows-Software-Development-Kit(SDK).php http://www.freyrscada.com/iec-60870-5-104-Linux-Software-Development-Kit(SDK).php firstname.lastname@example.org
JQM - Java Quine McCluskey for minimization of Boolean functions.
Java Quine McCluskey implements the Quine McCluskey algorithm with Petrick’s Method (or the method of prime implicants) for minimization of Boolean functions. This software can be used both for learning and solving real problems. As learning/teaching tool it presents not only the results, but also how the problem was solved as well as how to use Karnaugh Maps to solve the problem. Up to sixteen functions of sixteen variables can be minimized. A graphical interface is provided for entering and editing the truth table that can be saved and loaded. The results can be exported in HTML format. It generates the Karnaugh Map for educational purpose and the actual truth table from the obtained expressions even when multiple solutions for each function are found. This implementation supports PLC programming, so results can be presented in many forms including Structured Text (ST) and Ladder Diagram (LD) along conventional Boolean expression.
Integrated Development Environment (IDE) for learning HDL
UMHDL is an educational Integrated Development Environment (IDE) intended for learning digital designing with programmable logic devices using Hardware Description Languages (HDL) through simulation. It is an open-source application created at the Miguel Hernández University (UMH). The aim for the UMHDL development was to have a graphical application that allows learning the VHDL language without licensing restrictions (using some existing open-source tools) and requiring few resources. So, the interface developed acts as a front-end that allows writing code (with syntax highlighting), invokes an external VHDL compiler and simulator (such as GHDL), and displays the result of the simulation graphically as waveforms (invoking to GTKWave).
zamiaCAD is a modular and extensible platform for HW design, analysis, and research. It translates a HW description (VHDL or Verilog) into a language independent IG structure. Applications like a simulator and an eclipse GUI build on top of the IG.
Schematic circuit editor for VLSI and Mixed mode circuit simulation.
Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). The user interface is built with the Tcl-Tk toolkit, tcl is also the extension language used to send commands to the program. Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed.
This project provides a analog / mixed mode IC grade schematic capture tool with the accompanying netlisters.
ChronoSVG generates a timing diagram, as used in electrical devices documentations, from a simple and intuitive ASCII source file. The output file is in SVG format, and makes use of CSS to defer the styling details to presentation time.
Electric power system transient simulator
During the period from 1990 through 2002, EPRI funded the development of a Lightning Protection Design Workstation (LPDW), which was used by many utilities to assess the lightning performance of distribution lines. Since about 2002, this program has not been available. EPRI decided to release the simulation kernel of LPDW under an open-source license (GPL v3), so it may be incorporated into IEEE Flash and other projects. OpenETran can presently simulate multi-conductor power lines, insulators, surge arresters, non-linear grounds, and lightning strokes. It efficiently calculates energy and charge duty on surge arresters, and iterates to find the critical lightning current causing flashover on one or more phases. It is also suitable for use in substation insulation coordination. Capacitor switching, TRV, and other applicaitons may be added. EPRI originally had permission to use code from the Numerical Recipes book in LPDW. These routines have been removed in favor of GSL.
Timing-gen is a Linux tool to generate high quality Postscript timing diagrams from text input files.
Convert DXF drawings of circuit boards to gEDA-PCB files.
This Python script reads in a DXF (ascii) file and generates a PCB output compatible with PCB Designer, part of the gEDA suite. It is designed for two purposes: One is to generate a PCB snippet from a mechanical drawing (such as a board outline), the other is to produce element files from CAD drawings. PCB snippets are easily imported into an existing gEDA-PCB project using File -> Load Layout to Buffer. Generated element files are ready to use (except for special cases like no-paste flags and rounded pads).
Kicad shematic library manager
This is a first release of kicad schematic library manager. With this manager new schematic symbols can be created and or modified using spread sheet. The informations of component as description, documentation etc. can be modified as well. This manager enables moving components from one library to another one. The project source sode is hosted on: https://github.com/Filip83/kicad-lib-utils
Automatic coloring PCB - make a color circuit board for installation.
The program is designed for automatic coloring schemes of printed circuit boards for ease of installation. For its work requires some files with information on the printed circuit board, package generated by P-CAD. The basic principle: each type of component (identical components) are marked with a unique symbol that has its own color and style. This simplifies the visual search component on the board. The program also generates a text list of components, where the marks, what type of components is associated with which character on the circuit board.
A tool to simulate, draw and plot electrical power trees
Simulate the voltage and current up to the steady state Show components working out of specification Draw a nice power tree diagram showing the currents/powers balance Plot node transient voltage and gate current waveforms Change component parameters interactively to improve the design