Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

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  • ngspice Icon

    ngspice

    Ngspice project aims to improve the spice3f5 circuit simulator.

  • Printed Circuit Board Layout Tool Icon

    Printed Circuit Board Layout Tool

    PCB is a tool for the layout of printed circuit boards. PCB can produce industry standard RS-274X and Excellon NC-Drill format output for submission to board manufacturers.

  • adms Icon

    adms

    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

  • Electronic component analysis/synthesis

    Wcalc is a tool for the analysis and synthesis of electronic components. Some of the models include coupled microstrip lines, single layer air core solenoid inductors, etc. Wcalc can analyze the electrical parameters based on the physical dimensions a

  • Alliance CAD System

    Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.

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  • The PEP tool

    PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

  • Open SystemC Initiative (OSCI)

    The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification

    Downloads: 5 This Week Last Update: See Project
  • ArchC Architecture Description Language

    ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

    Downloads: 3 This Week Last Update: See Project
  • Visual STG Lab

    VSTGL is a graphical editor for Signal Transition Graphs (STG) and Petri nets. VSTGL is able to export the created STG to Petrify - an advanced tool for analyzing and optimizing STG's - or run Petrify on the graph directly.

    Downloads: 2 This Week Last Update: See Project
  • Cadence-Perforce Interface

    Advanced Software Configuration Management (SCM) for Cadence DFII. Delivers full Perforce capability to Cadence DFII using Best Practices for SCM. Please see http://public.perforce.com/public/perforce/cdsp4/index.html

    Downloads: 1 This Week Last Update: See Project
  • ECL Language and Compiler

    ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.

    Downloads: 1 This Week Last Update: See Project
  • MGEN/PARIS IC Design Environment

    The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.

    Downloads: 1 This Week Last Update: See Project
  • MP4Free

    The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

    Downloads: 1 This Week Last Update: See Project
  • C++ Template Classes of MVL

    C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.

    Downloads: 0 This Week Last Update: See Project
  • CapsimTMK

    Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

    Downloads: 0 This Week Last Update: See Project
  • ChipVault

    ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.

    Downloads: 0 This Week Last Update: See Project
  • G2C, LandGML to LandXML transform

    G2C (Geospatial to Civil) The LandGML Interoperability Experiment initiated by Autodesk, U.S. Army Corps of Engineers Engineering Research and Development Center, and Galdos Systems. this open source tool transforms LandGML into LandXML documents.

    Downloads: 0 This Week Last Update: See Project
  • IEEE 1532-compliant JTAG programmer

    This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!

    Downloads: 0 This Week Last Update: See Project
  • Java Decision Diagram Libraries (BDD)

    Java Decision Diagrams (BDD) libraries: JDD and JBDD

    This project used to contain two decision diagrams libraries: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD Both projects have now been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home If you are wondering why the move was made after 14 years (!!) on SourceForge, I suggest you read this article: http://arstechnica.com/information-technology/2015/05/sourceforge-grabs-gimp-for-windows-account-wraps-installer-in-bundle-pushing-adware/

    Downloads: 0 This Week Last Update: See Project
  • MMI Software Tools Public Domain Version

    IC CAD tools, documentation, scripts, and libraries for designing high-performance ICs, including SUE for schematics, MAX for layouts, DPC for datapaths and MCC for megacells. Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.

    Downloads: 0 This Week Last Update: See Project
  • ManifestParse

    An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.

    Downloads: 0 This Week Last Update: See Project
  • SPICE4

    Call for the specifications of (next generation of spice) spice4. The concept of spice kernel is proposed. The main function of spice kernel is to provide a communication between "application layer" and "low-level Algorithm layer".

  • Source Navigator for Verilog

    Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav

    Downloads: 0 This Week Last Update: See Project
  • Synopsys Consultant Script Repository

    An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.

    Downloads: 0 This Week Last Update: See Project
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    SystemC-WMS

    SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).

    Downloads: 0 This Week Last Update: See Project
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