Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

  • Focus on your Business with an integrated Business Cloud Focus on your Business with an integrated Business Cloud Icon
    Focus on your Business with an integrated Business Cloud Icon

    Reliable & Secure Business Phone Systems

    • No contracts, no cancellation fees, over 40 features
    • 99.999% financially backed uptime SLA
    • Free, expert support, certified by J.D. Power
  • Printed Circuit Board Layout Tool Icon

    Printed Circuit Board Layout Tool

    PCB is a tool for the layout of printed circuit boards. PCB can produce industry standard RS-274X and Excellon NC-Drill format output for submission to board manufacturers.

  • Electronic component analysis/synthesis

    Wcalc is a tool for the analysis and synthesis of electronic components. Some of the models include coupled microstrip lines, single layer air core solenoid inductors, etc. Wcalc can analyze the electrical parameters based on the physical dimensions a

  • XSCHEM Icon

    XSCHEM

    Schematic circuit editor for VLSI and Mixed mode circuit simulation.

    Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). The user interface is built with the Tcl-Tk toolkit, tcl is also the extension language used to send commands to the program. Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed.

    Downloads: 12 This Week Last Update: See Project
  • ManifestParse

    An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.

    Downloads: 0 This Week Last Update: See Project
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