Electronic Design Automation (EDA) Software

OS OS

    • More...
  • More...

Category Category

License License

    • More...

Translations Translations

Programming Language Programming Language

  • More...

Status Status

  • More...

Audience Audience

User Interface User Interface

  • More...

Freshness Freshness

Electronic Design Automation (EDA) Software

  • WhatsUp® Gold - Ranked #1 For Network Monitoring WhatsUp® Gold - Ranked #1 For Network Monitoring Icon
    WhatsUp® Gold - Ranked #1 For Network Monitoring Icon

    Automatically discover anything connected to your network with the industry's best flexible licensing. Free trial of our award-winning software

    The industry’s best network monitoring software, WhatsUp® Gold includes: Hybrid Cloud Monitoring, Real-Time Performance Monitoring, Automatic and Manual Failover and Extended Visibility to Distributed Networks. Trusted by thousands of organizations worldwide. WhatsUp® Gold - More Visibility. Better Performance. Less Cost. Try it free for 30 days.
    1/2
    How many devices do you monitor on your company's network?
    2/2
    One last question before you visit our site:

    When do you plan to purchase a network performance monitoring solution?
  • Multi-vendor storage monitoring simplified Multi-vendor storage monitoring simplified Icon
    Multi-vendor storage monitoring simplified Icon

    Monitor your multi-vendor storage to help ensure your applications get the performance and capacity they need with SolarWinds® Storage Resource Monito

    SolarWinds Storage Resource Monitor (SRM) gives you multi-vendor storage performance monitoring and alerting to help ensure peak storage performance. Automated capacity planning helps you predict storage shortages, reclaim space, and prevent application outages. SRM integrates with other Orion® Platform products to provide end-to-end visibility into the application stack, and lets you easily troubleshoot performance issues from application to storage.
  • ngspice Icon

    ngspice

    Ngspice project aims to improve the spice3f5 circuit simulator.

  • Printed Circuit Board Layout Tool Icon

    Printed Circuit Board Layout Tool

    PCB is a tool for the layout of printed circuit boards. PCB can produce industry standard RS-274X and Excellon NC-Drill format output for submission to board manufacturers.

  • adms Icon

    adms

    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git

  • Electronic component analysis/synthesis

    Wcalc is a tool for the analysis and synthesis of electronic components. Some of the models include coupled microstrip lines, single layer air core solenoid inductors, etc. Wcalc can analyze the electrical parameters based on the physical dimensions a

  • The PEP tool

    PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)

  • Find out what (or who) is slowing down your network Find out what (or who) is slowing down your network Icon
    Find out what (or who) is slowing down your network Icon

    Get comprehensive network bandwidth analysis and performance monitoring with SolarWinds® Bandwidth Analyzer Pack.

    Network slow, but you don't know the cause? Use Bandwidth Analyzer Pack (BAP) to monitor and analyze network bandwidth performance and traffic patterns. With BAP, you can identify which users, applications, and protocols are consuming the most bandwidth. You can also monitor Wireless LAN Controller traffic to see what applications and clients are using your wireless network. Try it free for 30 days!
  • Alliance CAD System

    Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.

  • Open SystemC Initiative (OSCI)

    The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification

    Downloads: 5 This Week Last Update: See Project
  • ArchC Architecture Description Language

    ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

    Downloads: 3 This Week Last Update: See Project
  • XSCHEM Icon

    XSCHEM

    Schematic circuit editor for VLSI and Mixed mode circuit simulation.

    Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit. Key feature of the program is its drawing engine written in C and using directly the Xlib drawing primitives; this gives top speed performance, even on very big circuits. I have succesfully managed to simulate complete VLSI projects with this tool, both digital (Verilog / VHDL) and analog (Spice). The user interface is built with the Tcl-Tk toolkit, tcl is also the extension language used to send commands to the program. Schematics can be printed in SVG, PNG, PDF, formats. XSCHEM runs on Linux or other Unix-likes with Xorg server and on Windows with the Cygwin layer and required tools installed.

    Downloads: 3 This Week Last Update: See Project
  • ECL Language and Compiler

    ECL is a system-level specification language for HW/SW designs and is based on Esterel and C. The ECL compiler parses ECL, writes Esterel and C, and uses the Esterel compiler to produce an implementation. Originally developed at Cadence Berkeley Labs.

    Downloads: 2 This Week Last Update: See Project
  • Communicate & Connect with Ring Central's VoIP Solution Communicate & Connect with Ring Central's VoIP Solution Icon
    Communicate & Connect with Ring Central's VoIP Solution Icon

    Cloud Powered Business Phone System

    • Unrivaled value & reliability in one solution
    • Unlimited Calls/SMS/Conferencing/Fax
    • Trusted by 350,000+ Businesses
  • Visual STG Lab

    VSTGL is a graphical editor for Signal Transition Graphs (STG) and Petri nets. VSTGL is able to export the created STG to Petrify - an advanced tool for analyzing and optimizing STG's - or run Petrify on the graph directly.

    Downloads: 2 This Week Last Update: See Project
  • Cadence-Perforce Interface

    Advanced Software Configuration Management (SCM) for Cadence DFII. Delivers full Perforce capability to Cadence DFII using Best Practices for SCM. Please see http://public.perforce.com/public/perforce/cdsp4/index.html

    Downloads: 1 This Week Last Update: See Project
  • CapsimTMK

    Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

    Downloads: 1 This Week Last Update: See Project
  • MGEN/PARIS IC Design Environment

    The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.

    Downloads: 1 This Week Last Update: See Project
  • MP4Free

    The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.

    Downloads: 1 This Week Last Update: See Project
  • Machet Digital Design Flow

    A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs. See the MediaWiki for more information on how to use it.

    Downloads: 1 This Week Last Update: See Project
  • C++ Template Classes of MVL

    C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.

    Downloads: 0 This Week Last Update: See Project
  • ChipVault

    ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.

    Downloads: 0 This Week Last Update: See Project
  • G2C, LandGML to LandXML transform

    G2C (Geospatial to Civil) The LandGML Interoperability Experiment initiated by Autodesk, U.S. Army Corps of Engineers Engineering Research and Development Center, and Galdos Systems. this open source tool transforms LandGML into LandXML documents.

    Downloads: 0 This Week Last Update: See Project
  • IEEE 1532-compliant JTAG programmer

    This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!

    Downloads: 0 This Week Last Update: See Project
  • MMI Software Tools Public Domain Version

    IC CAD tools, documentation, scripts, and libraries for designing high-performance ICs, including SUE for schematics, MAX for layouts, DPC for datapaths and MCC for megacells. Prebuilt binaries for Linux, Sparc-Solaris, and HP-PA.

    Downloads: 0 This Week Last Update: See Project
  • ManifestParse

    An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.

    Downloads: 0 This Week Last Update: See Project
  • SPICE4

    Call for the specifications of (next generation of spice) spice4. The concept of spice kernel is proposed. The main function of spice kernel is to provide a communication between "application layer" and "low-level Algorithm layer".

  • Source Navigator for Verilog

    Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav

    Downloads: 0 This Week Last Update: See Project
  • Synopsys Consultant Script Repository

    An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.

    Downloads: 0 This Week Last Update: See Project
  • Previous
  • You're on page 1
  • 2
  • Next

Get latest updates about Open Source Projects, Conferences and News.

No, Thank you