Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

  • Monitor your Cisco ASA like an expert Monitor your Cisco ASA like an expert Icon
    Monitor your Cisco ASA like an expert Icon

    See how Network Insight™ for Cisco® ASA, a feature of SolarWinds Network Performance Monitor and Network Configuration Manager, can help.

    Get visibility into the health and performance of your entire Cisco ASA environment in a single dashboard. View VPN tunnel status and monitor firewall high availability, health, and readiness. Automatically discover and filter within ACLs, show rule hit counts, and detect shadow and redundant rules. Automate the monitoring and management of your ASA infrastructure in a fully integrated solution. Try it free for 30 days!
  • Cloud Communications for Remote Teams Cloud Communications for Remote Teams Icon
    Cloud Communications for Remote Teams Icon

    Packed with Features to Support your Businesses Needs

    • 100% uptime, Patented design
    • Simple DIY Setup with Award Winning Support
    • Superior HD audio and video quality
  • SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing

    Downloads: 2 This Week Last Update: See Project
  • PLP

    Powerfull pre-processor

    Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)

    Downloads: 1 This Week Last Update: See Project
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