Ngspice project aims to improve the spice3f5 circuit simulator.
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
InSystem Serial Programmer Fujitsu MCU F2MC-16LX and FR series.
Open source C++ framework utilizing boost.org libraries and specialized for development of EDA applications.
Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered.
An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.
an open source software for electronic design automation (EDA).
OpenECAD is an open source software for electronic design automation (EDA / ECAD). OpenECAD integrates all stages of the design process: Schematic Capture, PCB layout, Component editing, CAM file generation. OpenECAD is cross-platform program, written with QT5 framework and run on Windows, Linux, and Mac OS X.
Generator for prefix graphs, which can be used to implement parallel prefix adders.
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).
Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.
IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
A back-end library for the use in creating an EDA application. The library includes Qt widgets that display schematic and PCB.
A program that generates PLD (Programmable Logic Device) programming tables & LFSR/BIBLO (Linear Feedback Shift Register/Built In Logic Block Observer) signature for a function given by the user.