Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

  • Reduce Support Costs with TeamSupport’s B2B helpdesk Reduce Support Costs with TeamSupport’s B2B helpdesk Icon
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  • See the Top 5 Processes in each line of business See the Top 5 Processes in each line of business Icon
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    Improve your workflow by getting familiar with how Intelligent Process Automation eliminates busywork across multiple departments.

    Process inefficiencies are a drain on any business, no matter how big or small, so speeding up your workflow is an absolute essential. Download the FREE Top 5 Process guides to better understand how workflow automation looks within each line of business like IT, Sales, Finance, and Human Resources. Remember, just because you’ve established a process within your organization or department, it doesn’t mean that it’s working as well as it could be.
  • QConsole

    QConsole is a custom Qt widget implementing a standard console to be inherited to support a specific scripting language or shell, and then embedded in any Qt application. As example, a Tcl console (QtclConsole) is provided for use in EDA applications

    Downloads: 6 This Week Last Update: See Project
  • ArchC Architecture Description Language

    ArchC is an open-source architecture description language based on SystemC. Its goal is to provide designers with a tool to evaluate new ideas in processor and ISA design, memory hierarchy, etc. and other aspects of computer architecture research.

    Downloads: 4 This Week Last Update: See Project
  • A UPF script 2 CPF script converter

    upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.

  • CDL cycle language, compiler, simulator

    Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.

    Downloads: 0 This Week Last Update: See Project
  • CapsimTMK

    Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.

    Downloads: 0 This Week Last Update: See Project
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  • Carrion

    This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.

    Downloads: 0 This Week Last Update: See Project
  • Eagle Technology Data Acquisition

    Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.

    Downloads: 0 This Week Last Update: See Project
  • Heat Exchanger Design

    The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and

    Downloads: 0 This Week Last Update: See Project
  • Hydrogix-System

    The idea of this project is automatize hydrogen Booster system created by Stanley Meyer to implement it in cars,trucks and electric plants as well as for production of free energy.

    Downloads: 0 This Week Last Update: See Project
  • JTLV - formal framework

    Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. JTLV is a new tool aimed to facilitate and provide a unified framework to the development of formal verification algorithms.

    Downloads: 0 This Week Last Update: See Project
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    Identify and respond to threats before damage is done Icon

    A SIEM that makes it easy to use logs for security, compliance, and troubleshooting.

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  • MGEN/PARIS IC Design Environment

    The comprehensive C++ library MGEN for IC layout and connectivity comes with the X11/Motif full custom layout editor PARIS and the powerful waveform viewer/processor MANIAC. Industry proven, it is the basis for layout generators, placers, routers etc.

    Downloads: 0 This Week Last Update: See Project
  • ManifestParse

    An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.

    Downloads: 0 This Week Last Update: See Project
  • Peripherals On Demand (POD)

    This (Python) tool allows you to easily create FPGA bitfiles for your embedded system, from several Open Source IPs (compatibles with the OpenCores Wishbone bus) . It will also generates the corresponding drivers (currently only Linux ones).

    Downloads: 0 This Week Last Update: See Project
  • PhiCAD

    PhiCAD is a LGPL'd , cross-platform software intended to provide to community an eclectic suite of CAD such as EDA to solve physics problems.

    Downloads: 0 This Week Last Update: See Project
  • Reaper ECAD libraries

    Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.

    Downloads: 0 This Week Last Update: See Project
  • Silicis- formal [verification] framework

    Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.

    Downloads: 0 This Week Last Update: See Project
  • Skidbladnir

    toolbox with information and programs for Computer Aided Innovation The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.

    Downloads: 0 This Week Last Update: See Project
  • V2000 Project

    Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.

    Downloads: 0 This Week Last Update: See Project
  • VeSpi

    VeSpi is a Verilog to SPICE netlist conversion tool. It takes structural Verilog as input and produces an equivalent SPICE netlist compatible with Berkeley SPICE. This allows a designer to check analog properties of a digital logic block.

    Downloads: 0 This Week Last Update: See Project
  • VoluMill client

    Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.

    Downloads: 0 This Week Last Update: See Project
  • oEDA

    A back-end library for the use in creating an EDA application. The library includes Qt widgets that display schematic and PCB.

    Downloads: 0 This Week Last Update: See Project
  • oagen

    Oagen enables the use of Open Access PCells in a Cadence DFII Framework where Open Access is not supported.

    Downloads: 0 This Week Last Update: See Project
  • pySoc

    System on Chip design generator.

    Downloads: 0 This Week Last Update: See Project
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