The MP4Free project provides a simulation, analysis and exploration platform for multi-processor system-on-chip applications at variable level of abstraction, providing also a comprehensive component library.
multilevel multiway circuit partitioning tool
KFilter is an application to design acoustic hifi loudspeakers in a theoretical way. It provides an interactive analysis of the equivalent analogue circuit design.
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
Verilog2C++: A translater from Verilog to C++
gdcsim is a modular logic circuit simulator that can run unattended. It detects faults such as glitches and race conditions.
gSXprog is used with the Parallax SX-Key or SX-Blitz to program Ubicom (formerly Scenix) SX microcontrollers.
ViPEC is an network analyser for electrical networks. It takes a schematic description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of port parameters (S, Y and Z).
Blitzer is a simple tool for driving the SX-Blitz microcontroller programmer from Parallax. There is now a version for PalmOS devices.
An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
Production (3 level) Programmer for Microchip PIC on Win9X,DOS,NT,Win2K. Flash and Eprom, 14 and 12 bit devices. Printer Port programmers and the BEL In-circuit Dual PRODUCTION Pic Programmer board.
Boardstatus is a Web-CGI/Postgresql database to manage electronic prototypes, including butch lists, notes, and and parameters. Support for users with different authorizations is included.
This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.
The purpose of the project is to design a methodology for making Application Specific Instruction set Processors. The project is a part of the Embedded Systems project in IIT-Delhi
ReliaFree is a Python and PyGTK based suite of tools to assist in Reliability, Availability, Maintainability, and Safety (RAMS) analyses. ReliaFree is intended to be an Open Source alternative to proprietary RAMS analyses solutions.
A very fast, yet accurate Transmission Line Calculator, suitable for silicon (Si+SiO2) substrates. The results are within +- 1% (in most cases) of those calculated by popular 2.5D-3D full wave simulators, while being orders of magnitude (7-8) faster.
Libraries and sample code for accessing remote toolpath delivery services such as VoluMill. Although much of the code is specific to the VoluMill service, it also defines open standards for exchanging toolpath information, parameters, and geometry.
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
A back-end library for the use in creating an EDA application. The library includes Qt widgets that display schematic and PCB.
The purpose of this project is to create a framework for automatically computing , symbolically, low entry expressions for linear circuits using R.D. Middlebrook's Extra Element Theorem.
Oagen enables the use of Open Access PCells in a Cadence DFII Framework where Open Access is not supported.
A program that analyzes info about an automotive engine, and wanted power increase in horsepower and the program helps give the user a possible turbocharger that satisfies the requirements.
Generator for prefix graphs, which can be used to implement parallel prefix adders.
DICaD is a free EDA software for VLSI circuits design.