Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered.
This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.
ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.
ChronoSVG generates a timing diagram, as used in electrical devices documentations, from a simple and intuitive ASCII source file. The output file is in SVG format, and makes use of CSS to defer the styling details to presentation time.
"kdiv" is a generator of routines for optimized division by an integer constant based on the work presented in H.S. Warren's "Hacker's Delight". "kdiv" can be used to emit a generic assembly or C implementation of (signed/unsigned) division.
Crushed bee Zigbee/Ethernet project: Goal become a software-hardware reference project for Zigbee/Ethernet SCADA system.
DICaD is a free EDA software for VLSI circuits design.
"DSO" is a Digital Signal Oscilloscope. My DSO will be connected via the USB to the PC. All software to operate the DSO is developed within this project.
The Daedalus Design framework is a complete design flow for multi-media embedded Multi-processor System-on-Chip (MPSoC) platforms. It transforms a high level system description into an FPGA prototype in a largely automated way in only a matter of hours.
ChNIDAQ allows user programs to use the NI-DAQ C library and run interpretively without compilation. It is an ideal solution for teaching and learning data acquisition, prototyping, and web-based remote data acquisition.
Dinotrace is a Verilog/VHDL waveform viewer for logic design traces for Linux/Windows X11. It includes color highlighting and back annotation of trace values onto source code inside Emacs. Please see www.veripool.org/dinotrace for lastest tarballs.
A suite of calculators and conversion tools for engineers.
Includes a signal scaling app, many engineering unit conversion calcs, and a task list pad to keep track of progress or notes.
Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
Embedded Systems are mostly used for highly sofisticated gadget used by Space Engineers and funded by armed forces. But the same concept can be used to create cool toys.
Experimental Boundary Scan (EBS) project provides software (driver + application) support to JTAG/IEEE 1149.1 boundary scan master (BSM) controllers under the Linux OS.
The purpose of this project is to create a framework for automatically computing , symbolically, low entry expressions for linear circuits using R.D. Middlebrook's Extra Element Theorem.
Language used: c++ Libraries used: fltk OS: Linux Problem Description: Jtag management software for CPLD and jtag aware chips Major features: X11 UI, c++ platform for jtag apps Data formats: jtag, bsdl, binary Derived from existing project "jtag"
FXPyTurns-n-Layers is a graphical transformer and induction coil design aid. The application performs the physical design of the coils for transformer and induction coils to determine: the length/weight of wire required to wind a coil with the specified
FXTurns-n-Layers is a graphical transformer and induction coil design aid. The program allows you to determine: the length (feet) and weight (lbs.) of wire needed to wind a coil. The program calculates the coil's finished dimensions and total resistance,
This project is a collection of field solver tools.
A GDSII Viewer that reads a standard GDSII file format and displays the contents of the file in a graphical format. It allows the viewer to zoom and pan the contents of the file.
This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.
A GTK+/Gnome2 graphical front end for the IW3HEV Vector Network Analyzer, also has a signal generator, and It displays graphicaly SWR, Phase, Return Loss, X impedance, Serial resistance, |Z| Impedanze, and Inductance, and capacitance.
XAvrTools is an open source graphical frontend for development with Atmels AVR microcontrollers using the UISP download tool and the AVR-GCC C compiler for LINUX. It is written in C++ using KDevelop and the QT library. It will include a software wizard.