This program converts assembly code to verilog implementation
dark themed version of free Audacity sound editor
audacity-extra now provides a sleek dark themed version of the Audacity open source sound editor. The project experiments with Audacity variations. There's a vowel-sound target-practice display for language learners and an analog waveform data logger for embedded systems.
A high-level electronic system level design and verification tool. SystemC is the language of choice used in system modelling. Highly pluggable design allows community supported SystemC model integration and a powerful GUI based design mechanism.
Open source C++ framework utilizing boost.org libraries and specialized for development of EDA applications.
is a Qt program to generate SMD chip shooter code
Still struggling with Excel to setup your pick and place machine ? Cad2Board reads component mounting information from Eagle, Altium Designer and Mentor Expedition PCB designs. Component or component groups can be assigned to feeder slots by drag and drop. Any modifications for PCB population can be defined to generate PCB variants, consider rotations from unusual tape and reel packaging or to account in advance for CAD library or PCB design bugs. Generated setup data is stored in a seperate project file. Succeeding PCB revisions what contain redesign changes can be merged with existing project setup data. Inconsistencies are highlighted to solve them by new assignements and unused feeders can be cleaned up with a single push. Finally a machine program is generated in Heeb HE50 format and downloaded to the machine interface.
CBOLD is a C++ framework for schematicless capture of board-level electronic designs. CBOLD replaces schematic capture EDA software in the traditional PCB design flow.
"cif2tribes" is a console-based tool for converting integrated circuit layouts into maps usable in the game Tribes 2, as a 3D visualization aid. The project code is modular enough to be easily extended to different game engines and input file formats.
CNF-toolkit is a simple library for constructing and manipulating boolean formulae in conjunctive normal form.
Caneda (Circuits and Networks EDA) is an open source EDA software.
Caneda (Circuits and Networks EDA) is an open source EDA software focused on easy of use and portability. While in the short term schematic capture and simulation is the primary goal, in the long term future, PCB and layout edition will be covered.
Capind is a program for calculating RLGC matrix of multi-conductor transmission lines of arbitrary shape and dielectric configuration. Capind is based on finite difference method and features easy-to-use input files and optional graphical interface.
Circuit simulators like SPICE for low memory computers
SPECI-SPICE is a subset of SPICE intended to run on low powered computers like Amstrad CPC, ZX Spectrum, CP/M machines, old PC machines, some programmable calculators,etc. by keeping most important functionality of SPICE 2.
This project is a collection of tools that are useful for someone working in the computer engineering field. So far this program is able to do logic minimization using the Quine-McClusky Method, numeric base conversion, and some bit manipulations.
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
The Decision Procedure Toolkit (DPT) is a system of cooperating decision procedures for answering satisfiability queries. The DPT implementation in OCaml comprises a DPLL-style SAT solver with theory-specific decision procedures.
EDAEd is Java-Based applications to demonstrate aspects of EDA (Eletronic Design Automation). This tools aim to help students of this area to view in a pratical environment, basic tools for placement and routing and data structures envolved.
Electronics design automation (EDA) suite for design of electronic circuits and systems, simulation (through physical / semi-empirical methods) and PCB layout/fabrication tools. Includes a GUI interface, Unix-style command-line utilities and a C API.
FERMAT's SystemC Parser using Doxygen and Xerces-C++ XML
Eclipse-based plugin for HRT-HOOD and HRT-UML design for Hard Real Time Systems
F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.
Provides a GUI for two freely available electronic circuit simulation engines: NG-Spice and GNU-Cap.
Gerber2eps - A small program for converting Gerber RS-274D files to Encapsulated Postscript (EPS).
Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates.
Jove - The Open Verification Environment for the Java (TM) Platform