naga EDA devotes to provide useful electronic design tools in C++ and, especially, Python. The current release contains naga.Verilog, a Verilog parser. Please visit project homepage http://naga-eda.org for more information
An easy to use spice interface with GTK. This project allows to start and view the simultions with one or two click. It uses gschem for the schematics and ngspice as simulator.
TkGate is a event driven digital circuit simulator with a tcl/tk-based graphical editor. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design.
Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
A Windows finite element solver for low frequency 2D and axisymmetric magnetic problems with graphical pre- and post-processors.
GBTiler, a Gerber circuit board tiling program allows engineers, electronics hobbyists and other users with Gerber RS274X format files to "tile" or combine separate Gerber files -- circuit boards -- into a single, valid Gerber formatted file.
Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
Spice+ is a general-purpose circuit simulation program, based directly on SPICE 3F.5 from the University of California (Berkeley). An improved version of Spice for DOS, Windows and Linux. http://spicep.sourceforge.net
Community driven PCB Layout and Schematic capture software
PCB Layout and Schematic capture tool for Win/Linux/Mac. Source code at https://github.com/sergei-iliev/myNetPCB
The ASCO project aims to bring circuit optimization capabilities to existing SPICE simulators using a high-performance parallel differential evolution (DE) optimization algorithm. It supports Eldo, HSPICE, LTspice, Spectre, and Qucs.
libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
"Magic" VLSI layout tool and various incarnations of the Berkeley tools.
InSystem Serial Programmer Fujitsu MCU F2MC-16LX and FR series.
FidoCad is a Windows program for drawing electronic schematics and printed circuits.
An API for manipulating EDIF netlists in Java. We use this API to analyze netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. This material is based upon work supported by the National Science Foundation under Grant No. 0801876. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.
This program is a simulator/debugger for Atmel AVR flash microcontrollers, built with Motif (incompatible with Less Tiff). It has language independent interface. This version can almost fully simulates AT90S and ATmega series.
A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
"ncdr2cnc" - N/C Drill to CNC code (G-Code) is the simple utility, which converts N/C drill files to G-Code files (adopted to Turbo CNC).
Python Gerber to G-code converter
pyGerber2Gcode is a Pyhon based simple Gerber to G-code converter.
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.
IEC 104 server and client simulator, Source code Library, win, Linux
IEC 60870-5-104 FreyrSCADA offering 1) IEC104 Server Simulator 2) IEC104 Client Simulator 3) Static and Dynamic Libraries 4) IEC104 Source Code Library 5) Demo Kit (Raspberry Pi & BeagleBone Black) or Customer specific Hardware windows, Linux, QNX Download Evaluation Kit - IEC 60870-5-104 Development Bundle New updated Version of IEC 60870-5-104 Simulator & SDK (Software Development Kit) is available now. FreyrSCADA IEC-60870-5-104 Development Bundle v21.03.026 In the Development Bundle, We included IEC 60870-5-104 Server & Client Simulator, Windows & Linux SDK. http://www.freyrscada.com/iec-60870-5-104.php http://www.freyrscada.com/iec-60870-5-104-Server-Simulator.php http://www.freyrscada.com/iec-60870-5-104-Client-Simulator.php http://www.freyrscada.com/iec-60870-5-104-Windows-Software-Development-Kit(SDK).php http://www.freyrscada.com/iec-60870-5-104-Linux-Software-Development-Kit(SDK).php firstname.lastname@example.org
a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
Program for minimizing boolean functions not using Karnaugh K-maps
Logic function minimizer is a free open software, which is developed to solve the Digital Electronics design problems. Using Quine-McCluskey algorithm