I interested the general-purpose BACNET communication protocol controller card design in automation technology, with ARM7 or AVR processors to use .
STARS stands for: Simple Terminal Automation and Reporting System The goal of this project is to provide a simple terminal automation and reporting system for the petroleum and bulk terminal industry
OpenSCH is schematic & emulation software for prototyping electronics projects.
OpenDesigner borrows the best ideas from 3d modeling tools, drafting software, the internet and the opensource community to create a powerful and easy to use tool for designing in the real world.
Gica is a calculator dealing with arbitrary precision two's complement binary numbers.
Coil, transformer and filter design software with included FEM analysis.
A developing tool for TI CC243x including compiler, IDE and library.
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification
Qlogico is a digital circuit simulator. True table, manipulation of boolean expresions, schematic capture and simulation, finite state machines, table of transitions, VHDL.
C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.
Geometric Technology - Programs written for MicroStation CAD System design automation.
Visually build and simulate boolean logic circuits
Visually build boolean logic circuits and then simulate their operation. Create custom components from user-designed circuits. Written in Java for cross-platform functionality. NOTE: This project has moved to Bitbucket at http://bitbucket.org/kwellwood/circuitsandbox
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
Delphi project extending TSimpleGraph (www.delphiarea.com) functionality. It creates a framework for data vizualization applications like industrial monitoring systems, workflow designer, just to name a few.
asfpga is an assembler written for use in FPGA design. It can be easily modified for your instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version al
Signs is a development environment for hardware designs in VHDL and other hardware description languages. It provides synthesis and simulation tools which are fully integrated in an Eclipse plugin including graphical netlist and waveform viewers.
Simulate electric current density in any conductive plane shape described by a bitmap image.
Collection of tools for allowing CAD (Computer Aided Design) systems to interact with STEP (ISO 10303) data.