Integrator for gEDA (GPL EDA) Suites & Bridge gEDA to Kicad
Gschem-finalizer is free & open source EDA-tool to finalize gEDA-gschem schematic project. It integrates several programs such gEDA (gschem, gnetlist, and NG-SPICE), GNU a2ps, psutils, and some basic GNU/Linux or UNIX programs. This software is written based PHP language & running on GNU/LINUX OS variants & UNIX OS variants. Features: 1. Generate netlists (SPICE 3F5, GEDA PCB, Kicad PCB/EESchema) 2. Pre-testing (additional DRC) 3. Result multi-pages in single file PDF output compilation with operating point description. 4. "Smartly" generate SPICE netlist for analog, digital, or mixed analysis simulation. 5. Generate Kicad netlist from gEDA schematic format. & More... See the manual for more info (http://gschemfinalizer.sourceforge.net/) The example of results are available at http://sourceforge.net/projects/matrix14freeamp/files/
Heterogeneous System-on-Chip Platform
HSoC is an easy-to-use, well-documented, open source, SystemC-based, cycle-accurate virtual platform of heterogeneous shared memory-based multicore SoCs. Each HSoC components a) supports a clean interface, b) implements a separate library, and c) includes dedicated testbenches (unit testing). Large-scale system models can instantiate and connect objects from all HSoC libraries. Each object may also collect different types of monitoring data by invoking a monitoring library. The target users of this software includes mainly CS/EE professionals. Some experience with SoC design methodology and SystemC (e.g. reading the SystemC User Manual and/or running and understanding the examples) is required. This research has been co-financed through the Operational Program "Education and Lifelong Learning", Action Archimedes III and is co-financed by the EU (European Social Fund) and Greek national funds (NSRF 2007 - 2013).
Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.
Hantek DSO-2150 software (Voltcraft/Darkwire/Protek/Acetech e.t.c DSO-2090/2150/2250/5200A e.t.c)
This project is aimed to develop an Hardware Monitor & Protection System for PCs using PICmicros. This project is divided into two branches: the first one involves microcontroller's firmware, the second one software used to manage the PIC via COM po
MW and RF Harmonic Balance Simulator
Virtual instrumentation software, currently designed for modifying automobile engines. Intended as a modular framework to communicate with devices on an IO port (serial, parallel etc.) and allow a visual representation of the instrument.
The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and
cad-utils is a set of modules for designing electrical boards. These programs allow you to cut and place graphs which used to present the models of the original electrical schemes.
A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.
Software for homebrew USB logic analyzer hardware.
The idea of this project is automatize hydrogen Booster system created by Stanley Meyer to implement it in cars,trucks and electric plants as well as for production of free energy.
This is a collection of (hopefully) useful productivity enhancements of Mentor Graphics IC-Station tools
This is an IEEE 1532 compliant JTAG programmer for CPLDs, FPGAs and similar programmable logic devices. It is only starting; developers are welcome!
The developed graphical interface is based on the SKILL language which is a Lisp dialect used as a scripting language and PCell (Parameterized Cells) description language used in many EDA software suites by Cadence Design Systems.
IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.
Icarus Verilog Interactive on MacOSX
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
ICDPROG is a simple command line programmer for Microchip PIC controllers, using the Microchip ICD (in circuit debugger) as a programmer.
Integrated Circuit Design Software that quickly automates design of analog and digital circuits for use in schematics, device modelling, design re-use, architecture, signal processing and IC manufacture.
The official repository of JCSim is now hosted by github at https://github.com/almejo/jcsim JCSim is a fully functional Digital Circuit simulator written in Java. You can create and simulate simple (and not so simple) circuits in an easy way. It includes a basic set of gates, simple creation of new gates and simulation.
A program to reverse engineer JEDEC programming files for PLDs (Programmable Logic Devices). The first version of this program can handle simple PAL devices. Future versions will be able to reverse engineer CPLDs (Complex PLDs).
JQM - Java Quine McCluskey for minimization of Boolean functions.
Java Quine McCluskey implements the Quine McCluskey algorithm with Petrick’s Method (or the method of prime implicants) for minimization of Boolean functions. This software can be used both for learning and solving real problems. As learning/teaching tool it presents not only the results, but also how the problem was solved as well as how to use Karnaugh Maps to solve the problem. Up to sixteen functions of sixteen variables can be minimized. A graphical interface is provided for entering and editing the truth table that can be saved and loaded. The results can be exported in HTML format. It generates the Karnaugh Map for educational purpose and the actual truth table from the obtained expressions even when multiple solutions for each function are found. This implementation supports PLC programming, so results can be presented in many forms including Structured Text (ST) and Ladder Diagram (LD) along conventional Boolean expression.
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project used to contain two decision diagrams libraries: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD Both projects have now been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home If you are wondering why the move was made after 14 years (!!) on SourceForge, I suggest you read this article: http://arstechnica.com/information-technology/2015/05/sourceforge-grabs-gimp-for-windows-account-wraps-installer-in-bundle-pushing-adware/