Open Source Linux Electronic Design Automation (EDA) Software - Page 11

FXPyTurns-n-Layers is a graphical transformer and induction coil design aid. The application performs the physical design of the coils for transformer and induction coils to determine: the length/weight of wire required to wind a coil with the specified

FXtransformer Designer is a graphical design aid for both power and RF transformers. RF Design: Broadband, Single-Tuned, Double-Tuned.

FXTurns-n-Layers is a graphical transformer and induction coil design aid. The program allows you to determine: the length (feet) and weight (lbs.) of wire needed to wind a coil. The program calculates the coil's finished dimensions and total resistance,

This project is a collection of field solver tools.

This project provides the software for Flamingo electronic building blocks (FEBB).

F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.

This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has been bundled as an executable JAR file along with an application which reads a RTL file(s), dumps the design units and the reverts those back. Please refer to the document for the details of the available APIs. You need Java JRE 1.6.x or above in order to use this utility. Feel free to contact the support team for any assistance.

1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the contents in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)

G2C (Geospatial to Civil) The LandGML Interoperability Experiment initiated by Autodesk, U.S. Army Corps of Engineers Engineering Research and Development Center, and Galdos Systems. this open source tool transforms LandGML into LandXML documents.

A GDSII Viewer that reads a standard GDSII file format and displays the contents of the file in a graphical format. It allows the viewer to zoom and pan the contents of the file.

GEZEL is a cycle-based hardware description language. The GEZEL tools offer stand-alone - and cosimulation, and code-generation into VHDL code. User-defined library-block extensions in C++ allow to add new cosimulation/cosynthesis interfaces.

GLogic is a logic gate simulator for linux and an adaptation of the gLogic package....

The gEDA project is working on producing a full GPL'd suite of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production.

Gaphor is a UML modeling environment written in Python. Gaphor is small and very extensible. The repository is located at http://github.com/gaphor/gaphor.

A clearing house for various pieces of open source software which use the GenCAM data format for input or output of electronic interconnect (PWB, PCB, PWA, PCA) information.

GerbTool is a set of tools for modifying gerber and excellon drill files. GerbTool can be used to tile multiple gerber files as a single job, and can be run interactively or in batch mode.

Gnetman is primarily a netlist translator, capable of translating between formats such as VHDL, Verilog, and SPICE. Only structural gate-level netlists are supported. Various netlist manipulations are supported.

This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.

XAvrTools is an open source graphical frontend for development with Atmels AVR microcontrollers using the UISP download tool and the AVR-GCC C compiler for LINUX. It is written in C++ using KDevelop and the QT library. It will include a software wizard.

Grid-tools is a collection of scripts to aid in the submission of complex jobs to either Sun Grid Engine or LSF.

HSoC is a open source, SystemC-based, cycle-accurate virtual platform for heterogeneous shared memory-based multicore SoCs. Each HSoC component has a clean interface, implements a separate class, and includes regression tests. Large-scale models can be instantiated, by connecting objects from all HSoC libraries. Each object may collect data by invoking a monitoring library. The target users are CS/EE professionals. Some experience with SoC design methodology and SystemC (e.g. reading the SystemC user manual and/or running the examples) is required. To reference this work: M.D. Grammatikakis, A. Papagrigoriou, P. Petrakis, and G. Kornaros, "Monitoring-aware VP prototypeof heterogeneous NoC-based multicore SoCs", Digital System Design Conf. (DSD), 2013, pp. 497-504. Available from http://doi.ieeecomputersociety.org/10.1109/DSD.2013.59 This research has been co-financed through the National Project Archimedes III and is co-financed by the EU project FP7-vIrtical.

HSP16 is a Pesona-16 (http://www.mysem.com) microprocessor simulation and development environment written in C. HSP16 is capable to simulate and run unmodified Pesona-16 assembly.

Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.

A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.