Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

  • WhatsUp® Gold - Ranked #1 For Network Monitoring WhatsUp® Gold - Ranked #1 For Network Monitoring Icon
    WhatsUp® Gold - Ranked #1 For Network Monitoring Icon

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  • FidoCadJ Icon

    FidoCadJ

    Simple and intuitive 2D vector drawing for electronics and not only.

    A multiplatform vector drawing program with a complete library of electronic symbols. Schematics and drawings are stored in a very compact text format. There is no netlist concept behind the drawings (so no simulation, and this is a choice) but this allows a great graphical flexibility and ease of use, making FidoCadJ the perfect tool for exchange sketches in forum and newsgroup discussions with a few clicks. Drawings can be exported in several graphic formats, such as pdf. Follow the development live on Twitter: https://twitter.com/davbucci

  • Gaphor

    Gaphor is a UML modeling environment written in Python. Gaphor will be small and very extensible. The repository is located at http://github.com/amolenaar/gaphor.

  • tkgate

    TkGate is a event driven digital circuit simulator with a tcl/tk-based graphical editor. TkGate supports a wide range of primitive circuit elements as well as user-defined modules for hierarchical design.

    Downloads: 21 This Week Last Update: See Project
  • gPICLIB

    GNU PIC LIBRARY PROJECT The interest of this project is to develop a set of Libraries that are released in LGPL License to use to PIC microcontroler programming. Then any program resulted by this use would be a proprietary or free softwares.

    Downloads: 1 This Week Last Update: See Project
  • PikLoops: a code generator for delay

    PikLoops is a simple KDE program used to generate assembly time delays for Microchip microcontrolers using Microchip instructions.

    Downloads: 0 This Week Last Update: See Project
  • TestDrive Profiling Master Icon

    TestDrive Profiling Master

    Make your own virtual FPGA system and profile deeply with CI.

    TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your system design. It performs a seamless conversion to a real FPGA environment without any changes of your testing software. I hope you will accomplish a successful design with TestDrive Profiling Master. Q&A : clonextop@gmail.com

    Downloads: 0 This Week Last Update: See Project
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