Ngspice project aims to improve the spice3f5 circuit simulator.
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
Provides a GUI for two freely available electronic circuit simulation engines: NG-Spice and GNU-Cap.
At the moment its simple command line tool to create nice looking schematic libraries in kicad. I hope that it would be usefull for someone. dont need to click anything just write/paste pin names and thats it.
Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
Gerber2eps - A small program for converting Gerber RS-274D files to Encapsulated Postscript (EPS).
libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
InSystem Serial Programmer Fujitsu MCU F2MC-16LX and FR series.
CBOLD is a C++ framework for schematicless capture of board-level electronic designs. CBOLD replaces schematic capture EDA software in the traditional PCB design flow.
"cif2tribes" is a console-based tool for converting integrated circuit layouts into maps usable in the game Tribes 2, as a 3D visualization aid. The project code is modular enough to be easily extended to different game engines and input file formats.
CNF-toolkit is a simple library for constructing and manipulating boolean formulae in conjunctive normal form.
This project is a collection of tools that are useful for someone working in the computer engineering field. So far this program is able to do logic minimization using the Quine-McClusky Method, numeric base conversion, and some bit manipulations.
F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
Jove - The Open Verification Environment for the Java (TM) Platform
An Open Source Parser Library for parsing Verilog, System Verilog, EDIF and VHDL source files.
Open framework for the automated synthesis of integrated heterogeneous (analog and multi-domain) systems.
Simcas is a simple and very flexible analog simulator. SimCAS uses symbolic equations to define components and solves the net system by using a "Computer Algebra System" algorithm.
HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.
TEAL - C++ multithreaded library to verfiy verilog designs
VSYML is an automated symbolic simulator for VHDL designs.
A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.
A back-end library for the use in creating an EDA application. The library includes Qt widgets that display schematic and PCB.