A program by Frederik De Kegel, to control a model rail road with the Intellibox of Uhlenbrock and Modeltreno. Een programma van Frederik De Kegel, om een modeltrein te besturen met de Intellibox van Uhlenbrock en Modeltreno.
This is a Computer Aided Electronic Design tool. It features schematic capture, simulation and PCB layout for both analog and numerical componants with the help of Gnome.
XAvrTools is an open source graphical frontend for development with Atmels AVR microcontrollers using the UISP download tool and the AVR-GCC C compiler for LINUX. It is written in C++ using KDevelop and the QT library. It will include a software wizard.
Grid-tools is a collection of scripts to aid in the submission of complex jobs to either Sun Grid Engine or LSF.
Integrator for gEDA (GPL EDA) Suites & Bridge gEDA to Kicad
Gschem-finalizer is free & open source EDA-tool to finalize gEDA-gschem schematic project. It integrates several programs such gEDA (gschem, gnetlist, and NG-SPICE), GNU a2ps, psutils, and some basic GNU/Linux or UNIX programs. This software is written based PHP language & running on GNU/LINUX OS variants & UNIX OS variants. Features: 1. Generate netlists (SPICE 3F5, GEDA PCB, Kicad PCB/EESchema) 2. Pre-testing (additional DRC) 3. Result multi-pages in single file PDF output compilation with operating point description. 4. "Smartly" generate SPICE netlist for analog, digital, or mixed analysis simulation. 5. Generate Kicad netlist from gEDA schematic format. & More... See the manual for more info (http://gschemfinalizer.sourceforge.net/) The example of results are available at http://sourceforge.net/projects/matrix14freeamp/files/
HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
HSP16 is a Pesona-16 (http://www.mysem.com) microprocessor simulation and development environment written in C. HSP16 is capable to simulate and run unmodified Pesona-16 assembly.
Hierarchical VCD Viewer is new trace file viewer. It's based on Qt 3.3.4 (migrating to Qt 4.1) graphic library and its main feature is to provide a hierarchical view of VCD trace file.
The project targets the chemical engg. students and industry as an aid to the design of heat exchanger. It will be a study aid and shall be able to give te relimnary dessign to an expert before he starts and puts his expertise into it. Design,Rating and
A static timing analysis program written in C++. Cadence LEF/DEF definitions of circuit geometry and SDF definitions of circuit timing data of a synchronous circuit are compiled in order to generate timing constraints for non-zero skew circuit operation.
The idea of this project is automatize hydrogen Booster system created by Stanley Meyer to implement it in cars,trucks and electric plants as well as for production of free energy.
This project is developed for Full Customer Design Enviroment. Schematic Entry/SPICE/SPICE(RF)/Layout/Verilog-AMS Via /Verilog Via Will be included.
Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
The official repository of JCSim is now hosted by github at https://github.com/almejo/jcsim JCSim is a fully functional Digital Circuit simulator written in Java. You can create and simulate simple (and not so simple) circuits in an easy way. It includes a basic set of gates, simple creation of new gates and simulation.
A Java based Backus-Naur test API
Java Decision Diagrams (BDD) libraries: JDD and JBDD
This project used to contain two decision diagrams libraries: - JBDD: a Java interface to two popular BDD libraries, CUDD and BuDDy - JDD: a native Java library supporting BDD, Z-BDD Both projects have now been moved to bitbucket.org: - https://bitbucket.org/vahidi/jbdd/wiki/Home - https://bitbucket.org/vahidi/jdd/wiki/Home If you are wondering why the move was made after 14 years (!!) on SourceForge, I suggest you read this article: http://arstechnica.com/information-technology/2015/05/sourceforge-grabs-gimp-for-windows-account-wraps-installer-in-bundle-pushing-adware/
Juno - OpenVera (TM) to Jove Translator
Simulator and Optimizer for S-Parameter Schematics. (C++ Recreation of my C Diploma, mostly for my own programming pleasure)
EDA / PCB software to envelope and manufacture printed circuit boards
A program for viewing and printing scheme files of KiCad EDA.
Project management moved to SourceForge: http://sf.net/projects/kicad/
Black Boxes System Design and simulation with C++
LTProg is pindriver technology multi devices programmer througth the PC USB Port
Laboratory software for computer communication with interface board.
layout tool for multilayer PCB design