Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
decida is [de]vice & [ci]rcuit [d]ata [a]nalysis. It is used for electron device characterization, procedural simulation/analysis of electronic circuits, or more general data analysis tasks.
free CMS for electronic websites
Multicube Explorer is a design space exploration tool for supporting platform-based design.
Here are many materials related to my lectures. Electrical Network Analysis, DSP, Programming, Optical Fiber Systems.
An event based simulator of digital electronic circuits
NimpSim is a hardware description language. The aim is to cover both high level and low level descriptions with a single language running on the JVM, The description language is Scala (NimpSim is just a library). It outputs vcd files.
Register Interface Description tool
A tool to descibe sets of memory mapped registers and to generate different outputs, e.g. C header files, Verilog source code, HTML documets, from that description. This tool is written in Java and uses ANTLR for parsing and StringTemplates for output generation.
Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.
Vaster is a EDA tool. It creates SystemC Cycle Accurate model from VerilogHDL RTL Model.