Electronic Design Automation (EDA) Software

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Electronic Design Automation (EDA) Software

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  • bel_fft Icon

    bel_fft

    FFT co-processor in Verilog based on the KISS FFT

    bel_fft is a FFT co-processor that can calculate FFTs with arbitrary radix. It is a hardware implementation of the free software Kiss FFT ("Keep it simple, Stupid!"). The target was to allow a simple replacement of the software code with the hardware implementation. Therefore bel_fft comes with a software driver that is compatible with the Kiss FFT routines. bel_fft also has a modular architecture and allows interfacing different bus architectures. So far AMBA AXI, Altera's Avalon bus and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.

  • A UPF script 2 CPF script converter

    upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.

  • FPGA Build Tool

    Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.

    Downloads: 0 This Week Last Update: See Project
  • Orchestra, a SoC Generator

    The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.

    Downloads: 0 This Week Last Update: See Project
  • PCBL

    A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.

    Downloads: 0 This Week Last Update: See Project
  • Vcomp Verilog Compiler

    vcomp is a verilog compiler for x86 linux targets - it was a commercial product which is now in the process of being GPL'd

    Downloads: 0 This Week Last Update: See Project
  • pySoc

    System on Chip design generator.

    Downloads: 0 This Week Last Update: See Project
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