Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.
A collection of Perl scripts for digital design simulation and FPGA synthesis automation. It supports Verilog, VHDL and mixed language (Verilog + VHDL) designs. See the MediaWiki for more information on how to use it.
An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.