Eclipse-based IDE for design verification tasks
DVKit provides an Eclipse-based integrated development environment (IDE) for common design-verification tasks, such as developing SystemVerilog, C++, TCL, Python, and shell code
Yet Another JNI-D2XX Interface Project
A Java Native Interface (JNI) library suitable for communicating with a range of USB interface chips from FTDI via the D2XX driver. It currently supports OS X 10.10+ and Windows 7/8 x64. On OS X, the 64 bit JVM is supported. On Windows, support is limited to the 64 bit JVM (Java 1.8 is now 64 bit). Version 1.0 (In progress) --------------------------------- - Java 8 - SPI support and sample (via MPSSE)
Verilog 2005 synthesizable subset parser built on ANTLR framework. 3-nov-2014: latest release here: https://github.com/gburdell/parser
This program converts assembly code to verilog implementation
EDAEd is Java-Based applications to demonstrate aspects of EDA (Eletronic Design Automation). This tools aim to help students of this area to view in a pratical environment, basic tools for placement and routing and data structures envolved.
Eclipse-based plugin for HRT-HOOD and HRT-UML design for Hard Real Time Systems
Jove - The Open Verification Environment for the Java (TM) Platform
An HDL alternative to PCB graphical schematic capture tools.
PHDL is an HDL that functions as an alternative to mainstream graphical schematic capture tools. The language is compiled into a pcb netlist which can then be imported into a layout tool. We are currently on version 2.1 of the tool. We have created an eclipse plugin version of the tool as well as a standalone command-line based version. Both function identically and output a netlist that can be imported into a pcb layout tool. VHDL revolutionized how FPGA designs and digital logic circuits have been designed and captured and overcame many of the difficulties associated with the use of schematic editing tools. We believe the use of an HDL is also the way of the future when it comes to PCB design. The PHDL compiler automatically supports the output of PADS and Eagle netlists, and through extending a simple java class, users can generate a netlist in practically any format required by their choice of a layout tool.
This project is destinated to develop um sistem to make more easy projects to embebed sistems that uses FPGA or Microcontrolers, and the programation in many plataforms and languages. There is a IDE and a hardware system to develop some products.
QMod is a semi-analytic model of Out of Order processor performance. The project downloads include MathCAD worksheets, a cycle-based simulator in Java, and helper scripts. See home page for papers.
Open framework for the automated synthesis of integrated heterogeneous (analog and multi-domain) systems.
Currently, all existing formal tools are designed to serve as formal verifiers, using one implementation or another. NO tool is providing a global framework to develop algorithms. Silicis is a new formal framework for designing [verification] algorithms.
Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.
application for optimize process of fabric spreading, layout of garment patterns, garment cutting.