KTechlab is an IDE for microcontrollers and electronics.
Icarus Verilog is an open source Verilog compiler that supports the IEEE-1364 Verilog HDL including IEEE1364-2005 plus extensions.
A graphical Finite State Machine (FSM) designer.
A graphical tool for designing finite state machines and exporting them to Hardware Description Languages, such as VHDL, AHDL, Verilog, or Ragel/SMC files for C, C++, Objective-C, Java, Python, PHP, Perl, Lua code generation.
gpsim is an open sourced simulator for Microchip's PIC microcontrollers. It supports all three families of PICs: 12-bit, 14-bit, and 16-bit cores. See also gputils http://gputils.sourceforge.net/
The project development has been moved on GitHub https://github.com/pcb2gcode/pcb2gcode The GUI for pcb2gcode can be found here https://github.com/pcb2gcode/pcb2gcodeGUI pcb2gcode is a command-line tool for isolation, routing and drilling of PCBs that provides full support for both single- and double-sided boards. For more information, see http://sourceforge.net/apps/mediawiki/pcb2gcode/
The KontrollerLab is an IDE for developing software for Atmel(r) AVR(c) microcontrollers using the avr-gcc compiler, the uisp and the avrdude upload software.
A Binary Decision Diagram library, with : many highly efficient vectorized BDD operations, dynamic variable reordering, automated garbage collection, a C++ interface with automatic reference counting, and much more.
QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.
AUDio MEasurement System - multi-platfrom system for audio measurement through sound card in the PC. Incorporates Generator, Oscilloscope, FFT, Sweep frequency characteristic. Now it can be compiled and works under MSWindows and Linux.
SPICE netlist visualizer
NetlistViewer is a tool capable of loading netlists in text format (currently only SPICE netlists) and convert them in a schematic (i..e graphical) form.
PEP is a modelling and verification framework for parallel systems, providing a large number of different modelling languages and verification techniques (e.g. SDL, Petri nets and model checking)
Alliance CAD System is a free set of EDA tools and portable cell libraries for VLSI design. It covers the design flow from VHDL up to layout. It includes VHDL simulator, RTL synthesis, place and route, netlist extractor, DRC, layout editor.
MMTL, the Multilayer Multiconductor Transmission Line 2-D and 2.5-D electromagnetic modeling tool suite, generates transmission parameters and SPICE models from descriptions of electronics interconnect dimensions and materials properties.
FXtransformer Designer is a graphical design aid for both power and RF transformers. RF Design: Broadband, Single-Tuned, Double-Tuned.
This project is for converting PCB RS274X gerber files to RS274NGC Gcode files. Currently this software is in the early development stages. Currently working to simplify the program and improve reliability.
QConsole is a custom Qt widget implementing a standard console to be inherited to support a specific scripting language or shell, and then embedded in any Qt application. As example, a Tcl console (QtclConsole) is provided for use in EDA applications
Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
Motorola HC08 (especially MC68HC908JB8) monitor-mode programmer project. Includes hardware part (RS-232 programmer design in Eagle) and software part (in C++ for KDE/Qt).
The Open SystemC Initiative (OSCI) is a collaborative effort to support and advance SystemC as a de facto standard for system-level design. SystemC is an interoperable, C++ SoC/IP modeling platform for fast system-level design and verification
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
This is a tool developed by 2nd yr CSE B.Techs at IIT Guwahati.We have designed a software in C++ language which,given some design specifications of an analog amplifier generates a netlist file in the current folder which can be opened in LTSpice.
Superscalar processor simulator for in-order and out-of-order processors. It also simulates several configurations of multiprocessors. Currently only supports the MIPS instructions set.
Extensible and easy to use logic circuit simulator.
The sigrok project aims at creating a portable, cross-platform, Free/Libre/Open-Source signal analysis software suite that supports various device types, such as logic analyzers, MSOs, oscilloscopes, multimeters, LCR meters, sound level meters, thermometers, anemometers, light meters, dataloggers, function generators, power supplies, GPIB interfaces, and more.
ViPEC is an network analyser for electrical networks. It takes a schematic description of an electrical network, and performs a simulation of the circuit response in the frequency domain. Output is in the form of port parameters (S, Y and Z).