TinyCAD is a program for drawing electrical circuit diagrams commonly known as schematic drawings. It supports standard and custom symbol libraries. It supports PCB layout programs with several netlist formats and can also produce SPICE simulation netlists. It is also often used to draw one-line diagrams, block diagrams, and presentation drawings.
Qt based Veroboard, Perfboard, and PCB layout and routing application
Cross-platform software for producing Veroboard (stripboard), Perfboard, and single-sided PCB layouts. Automatically prevents short circuits and checks for open circuits. Interactive auto-routing. Import from a TinyCAD schematic, or specify the netlist graphically. Can produce PDF output for toner transfer. In-built tutorial. Built using the Qt cross platform library, and tested on 32-bit Linux, and on Windows 7 (32-bit and 64-bit). Precompiled versions available for Windows.
A sparse matrix solver for electric power systems, based on the KLU library from University of Florida.
Integrated Circuit Design Software that quickly automates design of analog and digital circuits for use in schematics, device modelling, design re-use, architecture, signal processing and IC manufacture.
Powerful Verilog Preprocessor. PLP stands for Perl Pre-processor. Perl is used as "control language" that is embedded in the Verilog code (or any other code) to generate code on the fly. It is used commonly as a Verilog pre-processor but can be used with any target/output language (C, C++, Java, VHDL, plain text etc)
SystemC-WMS (Wave Mixed Signal Simulator) is a class library that extends the standard SystemC kernel to allow modeling and simulation of complex systems comprising analog parts from heterogeneous domain (electrical, mechanical, thermal, ...).
wxArt2D gives wxWindows applications sophisticated vector drawing functionality. It is based on a framework supporting multiple views within a hierarchical document. Supports drawing & (Graph) editing. In-output in SVG, GDSII, XML, easy to extend.
Make your own virtual FPGA system and profile deeply with CI.
TestDrive Profiling Master is a free simulation software for Verilog/SystemVerilog and C/C++. It supports a CI (Continuous Integration) activity for H/W & S/W engineers' cooperation. Run by MS Windows environment, its use is governed by MIT License(Profiles) and LGPLv3(TestDrive Profiling Master). Based on the powerful compiler Verilator and GCC, TestDrive Profiling Master provides a totally free virtual FPGA system environment with various dynamic documents for profiling in deep on your...